dram_ctrl.cc (10245:70333502b9b5) dram_ctrl.cc (10246:e0e3efe3b1d5)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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91 // banks
92 banks.resize(ranksPerChannel);
93 actTicks.resize(ranksPerChannel);
94 for (size_t c = 0; c < ranksPerChannel; ++c) {
95 banks[c].resize(banksPerRank);
96 actTicks[c].resize(activationLimit, 0);
97 }
98
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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91 // banks
92 banks.resize(ranksPerChannel);
93 actTicks.resize(ranksPerChannel);
94 for (size_t c = 0; c < ranksPerChannel; ++c) {
95 banks[c].resize(banksPerRank);
96 actTicks[c].resize(activationLimit, 0);
97 }
98
99 // set the bank indices
100 for (int r = 0; r < ranksPerChannel; r++) {
101 for (int b = 0; b < banksPerRank; b++) {
102 banks[r][b].rank = r;
103 banks[r][b].bank = b;
104 }
105 }
106
99 // perform a basic check of the write thresholds
100 if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
101 fatal("Write buffer low threshold %d must be smaller than the "
102 "high threshold %d\n", p->write_low_thresh_perc,
103 p->write_high_thresh_perc);
104
105 // determine the rows per bank by looking at the total capacity
106 uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size());

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747 }
748
749 DPRINTF(DRAM, "Done\n");
750
751 return;
752}
753
754void
107 // perform a basic check of the write thresholds
108 if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
109 fatal("Write buffer low threshold %d must be smaller than the "
110 "high threshold %d\n", p->write_low_thresh_perc,
111 p->write_high_thresh_perc);
112
113 // determine the rows per bank by looking at the total capacity
114 uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size());

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755 }
756
757 DPRINTF(DRAM, "Done\n");
758
759 return;
760}
761
762void
755DRAMCtrl::activateBank(Tick act_tick, uint8_t rank, uint8_t bank,
756 uint32_t row, Bank& bank_ref)
763DRAMCtrl::activateBank(Bank& bank, Tick act_tick, uint32_t row)
757{
764{
758 assert(0 <= rank && rank < ranksPerChannel);
765 // get the rank index from the bank
766 uint8_t rank = bank.rank;
767
759 assert(actTicks[rank].size() == activationLimit);
760
761 DPRINTF(DRAM, "Activate at tick %d\n", act_tick);
762
763 // update the open row
768 assert(actTicks[rank].size() == activationLimit);
769
770 DPRINTF(DRAM, "Activate at tick %d\n", act_tick);
771
772 // update the open row
764 assert(bank_ref.openRow == Bank::NO_ROW);
765 bank_ref.openRow = row;
773 assert(bank.openRow == Bank::NO_ROW);
774 bank.openRow = row;
766
767 // start counting anew, this covers both the case when we
768 // auto-precharged, and when this access is forced to
769 // precharge
775
776 // start counting anew, this covers both the case when we
777 // auto-precharged, and when this access is forced to
778 // precharge
770 bank_ref.bytesAccessed = 0;
771 bank_ref.rowAccesses = 0;
779 bank.bytesAccessed = 0;
780 bank.rowAccesses = 0;
772
773 ++numBanksActive;
774 assert(numBanksActive <= banksPerRank * ranksPerChannel);
775
776 DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n",
777 act_tick, numBanksActive);
778
779 // The next access has to respect tRAS for this bank
781
782 ++numBanksActive;
783 assert(numBanksActive <= banksPerRank * ranksPerChannel);
784
785 DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n",
786 act_tick, numBanksActive);
787
788 // The next access has to respect tRAS for this bank
780 bank_ref.preAllowedAt = act_tick + tRAS;
789 bank.preAllowedAt = act_tick + tRAS;
781
782 // Respect the row-to-column command delay
790
791 // Respect the row-to-column command delay
783 bank_ref.colAllowedAt = act_tick + tRCD;
792 bank.colAllowedAt = act_tick + tRCD;
784
785 // start by enforcing tRRD
786 for(int i = 0; i < banksPerRank; i++) {
787 // next activate to any bank in this rank must not happen
788 // before tRRD
789 banks[rank][i].actAllowedAt = std::max(act_tick + tRRD,
790 banks[rank][i].actAllowedAt);
791 }

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917 }
918
919 // next we need to account for the delay in activating the
920 // page
921 Tick act_tick = std::max(bank.actAllowedAt, curTick());
922
923 // Record the activation and deal with all the global timing
924 // constraints caused be a new activation (tRRD and tXAW)
793
794 // start by enforcing tRRD
795 for(int i = 0; i < banksPerRank; i++) {
796 // next activate to any bank in this rank must not happen
797 // before tRRD
798 banks[rank][i].actAllowedAt = std::max(act_tick + tRRD,
799 banks[rank][i].actAllowedAt);
800 }

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926 }
927
928 // next we need to account for the delay in activating the
929 // page
930 Tick act_tick = std::max(bank.actAllowedAt, curTick());
931
932 // Record the activation and deal with all the global timing
933 // constraints caused be a new activation (tRRD and tXAW)
925 activateBank(act_tick, dram_pkt->rank, dram_pkt->bank,
926 dram_pkt->row, bank);
934 activateBank(bank, act_tick, dram_pkt->row);
927
928 // issue the command as early as possible
929 cmd_at = bank.colAllowedAt;
930 }
931
932 // we need to wait until the bus is available before we can issue
933 // the command
934 cmd_at = std::max(cmd_at, busBusyUntil - tCL);

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936 // issue the command as early as possible
937 cmd_at = bank.colAllowedAt;
938 }
939
940 // we need to wait until the bus is available before we can issue
941 // the command
942 cmd_at = std::max(cmd_at, busBusyUntil - tCL);

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