dram_ctrl.cc (10214:39eb5d4c400a) dram_ctrl.cc (10215:52d46098c1b6)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1037 if (row_hit)
1038 writeRowHits++;
1039 bytesWritten += burstSize;
1040 perBankWrBursts[dram_pkt->bankId]++;
1041 }
1042}
1043
1044void
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1037 if (row_hit)
1038 writeRowHits++;
1039 bytesWritten += burstSize;
1040 perBankWrBursts[dram_pkt->bankId]++;
1041 }
1042}
1043
1044void
1045DRAMCtrl::moveToRespQ()
1046{
1047 // Remove from read queue
1048 DRAMPacket* dram_pkt = readQueue.front();
1049 readQueue.pop_front();
1050
1051 // sanity check
1052 assert(dram_pkt->size <= burstSize);
1053
1054 // Insert into response queue sorted by readyTime
1055 // It will be sent back to the requestor at its
1056 // readyTime
1057 if (respQueue.empty()) {
1058 respQueue.push_front(dram_pkt);
1059 assert(!respondEvent.scheduled());
1060 assert(dram_pkt->readyTime >= curTick());
1061 schedule(respondEvent, dram_pkt->readyTime);
1062 } else {
1063 bool done = false;
1064 auto i = respQueue.begin();
1065 while (!done && i != respQueue.end()) {
1066 if ((*i)->readyTime > dram_pkt->readyTime) {
1067 respQueue.insert(i, dram_pkt);
1068 done = true;
1069 }
1070 ++i;
1071 }
1072
1073 if (!done)
1074 respQueue.push_back(dram_pkt);
1075
1076 assert(respondEvent.scheduled());
1077
1078 if (respQueue.front()->readyTime < respondEvent.when()) {
1079 assert(respQueue.front()->readyTime >= curTick());
1080 reschedule(respondEvent, respQueue.front()->readyTime);
1081 }
1082 }
1083}
1084
1085void
1086DRAMCtrl::processNextReqEvent()
1087{
1088 if (busState == READ_TO_WRITE) {
1089 DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
1090 "waiting\n", readsThisTime, readQueue.size());
1091
1092 // sample and reset the read-related stats as we are now
1093 // transitioning to writes, and all reads are done

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1147 // event for the next request
1148 return;
1149 }
1150 } else {
1151 // Figure out which read request goes next, and move it to the
1152 // front of the read queue
1153 chooseNext(readQueue);
1154
1045DRAMCtrl::processNextReqEvent()
1046{
1047 if (busState == READ_TO_WRITE) {
1048 DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
1049 "waiting\n", readsThisTime, readQueue.size());
1050
1051 // sample and reset the read-related stats as we are now
1052 // transitioning to writes, and all reads are done

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1106 // event for the next request
1107 return;
1108 }
1109 } else {
1110 // Figure out which read request goes next, and move it to the
1111 // front of the read queue
1112 chooseNext(readQueue);
1113
1155 doDRAMAccess(readQueue.front());
1114 DRAMPacket* dram_pkt = readQueue.front();
1156
1115
1116 doDRAMAccess(dram_pkt);
1117
1157 // At this point we're done dealing with the request
1118 // At this point we're done dealing with the request
1158 // It will be moved to a separate response queue with a
1159 // correct readyTime, and eventually be sent back at that
1160 // time
1161 moveToRespQ();
1119 readQueue.pop_front();
1162
1120
1121 // sanity check
1122 assert(dram_pkt->size <= burstSize);
1123 assert(dram_pkt->readyTime >= curTick());
1124
1125 // Insert into response queue. It will be sent back to the
1126 // requestor at its readyTime
1127 if (respQueue.empty()) {
1128 assert(!respondEvent.scheduled());
1129 schedule(respondEvent, dram_pkt->readyTime);
1130 } else {
1131 assert(respQueue.back()->readyTime <= dram_pkt->readyTime);
1132 assert(respondEvent.scheduled());
1133 }
1134
1135 respQueue.push_back(dram_pkt);
1136
1163 // we have so many writes that we have to transition
1164 if (writeQueue.size() > writeHighThreshold) {
1165 switch_to_writes = true;
1166 }
1167 }
1168
1169 // switching to writes, either because the read queue is empty
1170 // and the writes have passed the low threshold (or we are

--- 658 unchanged lines hidden --- 		1137 // we have so many writes that we have to transition
1138 if (writeQueue.size() > writeHighThreshold) {
1139 switch_to_writes = true;
1140 }
1141 }
1142
1143 // switching to writes, either because the read queue is empty
1144 // and the writes have passed the low threshold (or we are

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