dram_ctrl.cc (10211:e084db2b1527) dram_ctrl.cc (10212:acc1131e01d6)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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71 readBufferSize(p->read_buffer_size),
72 writeBufferSize(p->write_buffer_size),
73 writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
74 writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
75 minWritesPerSwitch(p->min_writes_per_switch),
76 writesThisTime(0), readsThisTime(0),
77 tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST),
78 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR),
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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71 readBufferSize(p->read_buffer_size),
72 writeBufferSize(p->write_buffer_size),
73 writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
74 writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
75 minWritesPerSwitch(p->min_writes_per_switch),
76 writesThisTime(0), readsThisTime(0),
77 tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST),
78 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR),
79 tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
79 tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
80 tXAW(p->tXAW), activationLimit(p->activation_limit),
81 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
82 pageMgmt(p->page_policy),
83 maxAccessesPerRow(p->max_accesses_per_row),
84 frontendLatency(p->static_frontend_latency),
85 backendLatency(p->static_backend_latency),
86 busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE),
87 pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0),

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555 "tCL %d ticks\n" \
556 "tRP %d ticks\n" \
557 "tBURST %d ticks\n" \
558 "tRFC %d ticks\n" \
559 "tREFI %d ticks\n" \
560 "tWTR %d ticks\n" \
561 "tRTW %d ticks\n" \
562 "tWR %d ticks\n" \
80 tXAW(p->tXAW), activationLimit(p->activation_limit),
81 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
82 pageMgmt(p->page_policy),
83 maxAccessesPerRow(p->max_accesses_per_row),
84 frontendLatency(p->static_frontend_latency),
85 backendLatency(p->static_backend_latency),
86 busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE),
87 pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), prevArrival(0),

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555 "tCL %d ticks\n" \
556 "tRP %d ticks\n" \
557 "tBURST %d ticks\n" \
558 "tRFC %d ticks\n" \
559 "tREFI %d ticks\n" \
560 "tWTR %d ticks\n" \
561 "tRTW %d ticks\n" \
562 "tWR %d ticks\n" \
563 "tRTP %d ticks\n" \
563 "tXAW (%d) %d ticks\n",
564 name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR,
564 "tXAW (%d) %d ticks\n",
565 name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR,
565 tRTW, tWR, activationLimit, tXAW);
566 tRTW, tWR, tRTP, activationLimit, tXAW);
566}
567
568void
569DRAMCtrl::printQs() const {
570 DPRINTF(DRAM, "===READ QUEUE===\n\n");
571 for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) {
572 DPRINTF(DRAM, "Read %lu\n", (*i)->addr);
573 }

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988
989 // only one burst can use the bus at any one point in time
990 assert(dram_pkt->readyTime - busBusyUntil >= tBURST);
991
992 // not strictly necessary, but update the time for the next
993 // read/write (add a max with tCCD here)
994 bank.colAllowedAt = cmd_at + tBURST;
995
567}
568
569void
570DRAMCtrl::printQs() const {
571 DPRINTF(DRAM, "===READ QUEUE===\n\n");
572 for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) {
573 DPRINTF(DRAM, "Read %lu\n", (*i)->addr);
574 }

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989
990 // only one burst can use the bus at any one point in time
991 assert(dram_pkt->readyTime - busBusyUntil >= tBURST);
992
993 // not strictly necessary, but update the time for the next
994 // read/write (add a max with tCCD here)
995 bank.colAllowedAt = cmd_at + tBURST;
996
996 // If this is a write, we also need to respect the write
997 // recovery time before a precharge
998 if (!dram_pkt->isRead) {
999 bank.preAllowedAt = std::max(bank.preAllowedAt,
1000 dram_pkt->readyTime + tWR);
1001 }
997 // If this is a write, we also need to respect the write recovery
998 // time before a precharge, in the case of a read, respect the
999 // read to precharge constraint
1000 bank.preAllowedAt = std::max(bank.preAllowedAt,
1001 dram_pkt->isRead ? cmd_at + tRTP :
1002 dram_pkt->readyTime + tWR);
1002
1003 // increment the bytes accessed and the accesses per row
1004 bank.bytesAccessed += burstSize;
1005 ++bank.rowAccesses;
1006
1007 // if we reached the max, then issue with an auto-precharge
1008 bool auto_precharge = pageMgmt == Enums::close ||
1009 bank.rowAccesses == maxAccessesPerRow;

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1004 // increment the bytes accessed and the accesses per row
1005 bank.bytesAccessed += burstSize;
1006 ++bank.rowAccesses;
1007
1008 // if we reached the max, then issue with an auto-precharge
1009 bool auto_precharge = pageMgmt == Enums::close ||
1010 bank.rowAccesses == maxAccessesPerRow;

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