dram_ctrl.cc (10146:27dfed4c8403) dram_ctrl.cc (10147:3e51a30b8071)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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65 rowBufferSize(devicesPerRank * deviceRowBufferSize),
66 columnsPerRowBuffer(rowBufferSize / burstSize),
67 ranksPerChannel(p->ranks_per_channel),
68 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
69 readBufferSize(p->read_buffer_size),
70 writeBufferSize(p->write_buffer_size),
71 writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
72 writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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65 rowBufferSize(devicesPerRank * deviceRowBufferSize),
66 columnsPerRowBuffer(rowBufferSize / burstSize),
67 ranksPerChannel(p->ranks_per_channel),
68 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
69 readBufferSize(p->read_buffer_size),
70 writeBufferSize(p->write_buffer_size),
71 writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
72 writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
73 minWritesPerSwitch(p->min_writes_per_switch), writesThisTime(0),
73 minWritesPerSwitch(p->min_writes_per_switch),
74 writesThisTime(0), readsThisTime(0),
74 tWTR(p->tWTR), tBURST(p->tBURST),
75 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
76 tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
77 tXAW(p->tXAW), activationLimit(p->activation_limit),
78 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
79 pageMgmt(p->page_policy),
80 maxAccessesPerRow(p->max_accesses_per_row),
81 frontendLatency(p->static_frontend_latency),

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394 DRAMPacket* dram_pkt = writeQueue.front();
395 // sanity check
396 assert(dram_pkt->size <= burstSize);
397 doDRAMAccess(dram_pkt);
398
399 writeQueue.pop_front();
400 delete dram_pkt;
401
75 tWTR(p->tWTR), tBURST(p->tBURST),
76 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
77 tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
78 tXAW(p->tXAW), activationLimit(p->activation_limit),
79 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
80 pageMgmt(p->page_policy),
81 maxAccessesPerRow(p->max_accesses_per_row),
82 frontendLatency(p->static_frontend_latency),

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395 DRAMPacket* dram_pkt = writeQueue.front();
396 // sanity check
397 assert(dram_pkt->size <= burstSize);
398 doDRAMAccess(dram_pkt);
399
400 writeQueue.pop_front();
401 delete dram_pkt;
402
402 ++writesThisTime;
403
404 DPRINTF(DRAM, "Writing, bus busy for %lld ticks, banks busy "
405 "for %lld ticks\n", busBusyUntil - temp1, maxBankFreeAt() - temp2);
406
403 DPRINTF(DRAM, "Writing, bus busy for %lld ticks, banks busy "
404 "for %lld ticks\n", busBusyUntil - temp1, maxBankFreeAt() - temp2);
405
407 // If we emptied the write queue, or got below the threshold and
406 // If we emptied the write queue, or got sufficiently below the
407 // threshold (using the minWritesPerSwitch as the hysteresis) and
408 // are not draining, or we have reads waiting and have done enough
409 // writes, then switch to reads. The retry above could already
410 // have caused it to be scheduled, so first check
411 if (writeQueue.empty() ||
408 // are not draining, or we have reads waiting and have done enough
409 // writes, then switch to reads. The retry above could already
410 // have caused it to be scheduled, so first check
411 if (writeQueue.empty() ||
412 (writeQueue.size() < writeLowThreshold && !drainManager) ||
412 (writeQueue.size() + minWritesPerSwitch < writeLowThreshold &&
413 !drainManager) ||
413 (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) {
414 // turn the bus back around for reads again
415 busBusyUntil += tWTR;
416 stopReads = false;
414 (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) {
415 // turn the bus back around for reads again
416 busBusyUntil += tWTR;
417 stopReads = false;
418
419 DPRINTF(DRAM, "Switching to reads after %d writes with %d writes "
420 "waiting\n", writesThisTime, writeQueue.size());
421
422 wrPerTurnAround.sample(writesThisTime);
417 writesThisTime = 0;
418
419 if (!nextReqEvent.scheduled())
420 schedule(nextReqEvent, busBusyUntil);
421 } else {
422 assert(!writeEvent.scheduled());
423 DPRINTF(DRAM, "Next write scheduled at %lld\n", newTime);
424 schedule(writeEvent, newTime);

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436 drainManager = NULL;
437 }
438}
439
440
441void
442DRAMCtrl::triggerWrites()
443{
423 writesThisTime = 0;
424
425 if (!nextReqEvent.scheduled())
426 schedule(nextReqEvent, busBusyUntil);
427 } else {
428 assert(!writeEvent.scheduled());
429 DPRINTF(DRAM, "Next write scheduled at %lld\n", newTime);
430 schedule(writeEvent, newTime);

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442 drainManager = NULL;
443 }
444}
445
446
447void
448DRAMCtrl::triggerWrites()
449{
444 DPRINTF(DRAM, "Writes triggered at %lld\n", curTick());
450 DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
451 "waiting\n", readsThisTime, readQueue.size());
452
445 // Flag variable to stop any more read scheduling
446 stopReads = true;
447
448 Tick write_start_time = std::max(busBusyUntil, curTick()) + tWTR;
449
450 DPRINTF(DRAM, "Writes scheduled at %lld\n", write_start_time);
451
453 // Flag variable to stop any more read scheduling
454 stopReads = true;
455
456 Tick write_start_time = std::max(busBusyUntil, curTick()) + tWTR;
457
458 DPRINTF(DRAM, "Writes scheduled at %lld\n", write_start_time);
459
460 // there is some danger here as there might still be reads
461 // happening before the switch actually takes place
462 rdPerTurnAround.sample(readsThisTime);
463 readsThisTime = 0;
464
452 assert(write_start_time >= curTick());
453 assert(!writeEvent.scheduled());
454 schedule(writeEvent, write_start_time);
455}
456
457void
458DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
459{

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1193 dram_pkt->readyTime - dram_pkt->entryTime);
1194
1195 // Update the minimum timing between the requests
1196 newTime = (busBusyUntil > tRP + tRCD + tCL) ?
1197 std::max(busBusyUntil - (tRP + tRCD + tCL), curTick()) : curTick();
1198
1199 // Update the access related stats
1200 if (dram_pkt->isRead) {
465 assert(write_start_time >= curTick());
466 assert(!writeEvent.scheduled());
467 schedule(writeEvent, write_start_time);
468}
469
470void
471DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
472{

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1206 dram_pkt->readyTime - dram_pkt->entryTime);
1207
1208 // Update the minimum timing between the requests
1209 newTime = (busBusyUntil > tRP + tRCD + tCL) ?
1210 std::max(busBusyUntil - (tRP + tRCD + tCL), curTick()) : curTick();
1211
1212 // Update the access related stats
1213 if (dram_pkt->isRead) {
1214 ++readsThisTime;
1201 if (rowHitFlag)
1202 readRowHits++;
1203 bytesReadDRAM += burstSize;
1204 perBankRdBursts[dram_pkt->bankId]++;
1205 } else {
1215 if (rowHitFlag)
1216 readRowHits++;
1217 bytesReadDRAM += burstSize;
1218 perBankRdBursts[dram_pkt->bankId]++;
1219 } else {
1220 ++writesThisTime;
1206 if (rowHitFlag)
1207 writeRowHits++;
1208 bytesWritten += burstSize;
1209 perBankWrBursts[dram_pkt->bankId]++;
1210
1211 // At this point, commonality between reads and writes ends.
1212 // For writes, we are done since we long ago responded to the
1213 // requestor.

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1513 .desc("What write queue length does an incoming req see");
1514
1515 bytesPerActivate
1516 .init(maxAccessesPerRow)
1517 .name(name() + ".bytesPerActivate")
1518 .desc("Bytes accessed per row activation")
1519 .flags(nozero);
1520
1221 if (rowHitFlag)
1222 writeRowHits++;
1223 bytesWritten += burstSize;
1224 perBankWrBursts[dram_pkt->bankId]++;
1225
1226 // At this point, commonality between reads and writes ends.
1227 // For writes, we are done since we long ago responded to the
1228 // requestor.

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1528 .desc("What write queue length does an incoming req see");
1529
1530 bytesPerActivate
1531 .init(maxAccessesPerRow)
1532 .name(name() + ".bytesPerActivate")
1533 .desc("Bytes accessed per row activation")
1534 .flags(nozero);
1535
1536 rdPerTurnAround
1537 .init(readBufferSize)
1538 .name(name() + ".rdPerTurnAround")
1539 .desc("Reads before turning the bus around for writes")
1540 .flags(nozero);
1541
1542 wrPerTurnAround
1543 .init(writeBufferSize)
1544 .name(name() + ".wrPerTurnAround")
1545 .desc("Writes before turning the bus around for reads")
1546 .flags(nozero);
1547
1521 bytesReadDRAM
1522 .name(name() + ".bytesReadDRAM")
1523 .desc("Total number of bytes read from DRAM");
1524
1525 bytesReadWrQ
1526 .name(name() + ".bytesReadWrQ")
1527 .desc("Total number of bytes read from write queue");
1528

--- 190 unchanged lines hidden --- 		1548 bytesReadDRAM
1549 .name(name() + ".bytesReadDRAM")
1550 .desc("Total number of bytes read from DRAM");
1551
1552 bytesReadWrQ
1553 .name(name() + ".bytesReadWrQ")
1554 .desc("Total number of bytes read from write queue");
1555

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