60c60
< port(name() + ".port", *this),
---
> port(name() + ".port", *this), isTimingMode(false),
242,243c242,243
< // timestamp offset should be in clock cycles for DRAMPower
< timeStampOffset = divCeil(curTick(), tCK);
---
> // remember the memory system mode of operation
> isTimingMode = system()->isTimingMode();
245,249c245,247
< // update the start tick for the precharge accounting to the
< // current tick
< for (auto r : ranks) {
< r->startup(curTick() + tREFI - tRP);
< }
---
> if (isTimingMode) {
> // timestamp offset should be in clock cycles for DRAMPower
> timeStampOffset = divCeil(curTick(), tCK);
251,255c249,260
< // shift the bus busy time sufficiently far ahead that we never
< // have to worry about negative values when computing the time for
< // the next request, this will add an insignificant bubble at the
< // start of simulation
< busBusyUntil = curTick() + tRP + tRCD + tCL;
---
> // update the start tick for the precharge accounting to the
> // current tick
> for (auto r : ranks) {
> r->startup(curTick() + tREFI - tRP);
> }
>
> // shift the bus busy time sufficiently far ahead that we never
> // have to worry about negative values when computing the time for
> // the next request, this will add an insignificant bubble at the
> // start of simulation
> busBusyUntil = curTick() + tRP + tRCD + tCL;
> }
1557a1563,1568
> DRAMCtrl::Rank::suspend()
> {
> deschedule(refreshEvent);
> }
>
> void
2199a2211,2229
> void
> DRAMCtrl::drainResume()
> {
> if (!isTimingMode && system()->isTimingMode()) {
> // if we switched to timing mode, kick things into action,
> // and behave as if we restored from a checkpoint
> startup();
> } else if (isTimingMode && !system()->isTimingMode()) {
> // if we switch from timing mode, stop the refresh events to
> // not cause issues with KVM
> for (auto r : ranks) {
> r->suspend();
> }
> }
>
> // update the mode
> isTimingMode = system()->isTimingMode();
> }
>