117a118,120
> // GDDR addressing of banks to BG is linear.
> // Here we assume that all DRAM generations address bank groups as
> // follows:
227c230,231
< if (tRRD_L <= tRRD) {
---
> // some datasheets might specify it equal to tRRD
> if (tRRD_L < tRRD) {
> // GDDR addressing of banks to BG is linear.
> // Here we assume that all DRAM generations address bank groups as
> // follows:
227c230,231
< if (tRRD_L <= tRRD) {
---
> // some datasheets might specify it equal to tRRD
> if (tRRD_L < tRRD) {