61 retryRdReq(false), retryWrReq(false), 62 busState(READ), 63 nextReqEvent(this), respondEvent(this), 64 drainManager(NULL), 65 deviceSize(p->device_size), 66 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 67 deviceRowBufferSize(p->device_rowbuffer_size), 68 devicesPerRank(p->devices_per_rank), 69 burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 70 rowBufferSize(devicesPerRank * deviceRowBufferSize), 71 columnsPerRowBuffer(rowBufferSize / burstSize), 72 columnsPerStripe(range.granularity() / burstSize), 73 ranksPerChannel(p->ranks_per_channel), 74 bankGroupsPerRank(p->bank_groups_per_rank), 75 bankGroupArch(p->bank_groups_per_rank > 0), 76 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 77 readBufferSize(p->read_buffer_size), 78 writeBufferSize(p->write_buffer_size), 79 writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 80 writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 81 minWritesPerSwitch(p->min_writes_per_switch), 82 writesThisTime(0), readsThisTime(0), 83 tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 84 tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 85 tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 86 tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit), 87 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 88 pageMgmt(p->page_policy), 89 maxAccessesPerRow(p->max_accesses_per_row), 90 frontendLatency(p->static_frontend_latency), 91 backendLatency(p->static_backend_latency), 92 busBusyUntil(0), prevArrival(0), 93 nextReqTime(0), activeRank(0), timeStampOffset(0) 94{ 95 for (int i = 0; i < ranksPerChannel; i++) { 96 Rank* rank = new Rank(*this, p); 97 ranks.push_back(rank); 98 99 rank->actTicks.resize(activationLimit, 0); 100 rank->banks.resize(banksPerRank); 101 rank->rank = i; 102 103 for (int b = 0; b < banksPerRank; b++) { 104 rank->banks[b].bank = b; 105 // GDDR addressing of banks to BG is linear. 106 // Here we assume that all DRAM generations address bank groups as 107 // follows: 108 if (bankGroupArch) { 109 // Simply assign lower bits to bank group in order to 110 // rotate across bank groups as banks are incremented 111 // e.g. with 4 banks per bank group and 16 banks total: 112 // banks 0,4,8,12 are in bank group 0 113 // banks 1,5,9,13 are in bank group 1 114 // banks 2,6,10,14 are in bank group 2 115 // banks 3,7,11,15 are in bank group 3 116 rank->banks[b].bankgr = b % bankGroupsPerRank; 117 } else { 118 // No bank groups; simply assign to bank number 119 rank->banks[b].bankgr = b; 120 } 121 } 122 } 123 124 // perform a basic check of the write thresholds 125 if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 126 fatal("Write buffer low threshold %d must be smaller than the " 127 "high threshold %d\n", p->write_low_thresh_perc, 128 p->write_high_thresh_perc); 129 130 // determine the rows per bank by looking at the total capacity 131 uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 132 133 // determine the dram actual capacity from the DRAM config in Mbytes 134 uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 135 ranksPerChannel; 136 137 // if actual DRAM size does not match memory capacity in system warn! 138 if (deviceCapacity != capacity / (1024 * 1024)) 139 warn("DRAM device capacity (%d Mbytes) does not match the " 140 "address range assigned (%d Mbytes)\n", deviceCapacity, 141 capacity / (1024 * 1024)); 142 143 DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 144 AbstractMemory::size()); 145 146 DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 147 rowBufferSize, columnsPerRowBuffer); 148 149 rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 150 151 // a bit of sanity checks on the interleaving 152 if (range.interleaved()) { 153 if (channels != range.stripes()) 154 fatal("%s has %d interleaved address stripes but %d channel(s)\n", 155 name(), range.stripes(), channels); 156 157 if (addrMapping == Enums::RoRaBaChCo) { 158 if (rowBufferSize != range.granularity()) { 159 fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 160 "address map\n", name()); 161 } 162 } else if (addrMapping == Enums::RoRaBaCoCh || 163 addrMapping == Enums::RoCoRaBaCh) { 164 // for the interleavings with channel bits in the bottom, 165 // if the system uses a channel striping granularity that 166 // is larger than the DRAM burst size, then map the 167 // sequential accesses within a stripe to a number of 168 // columns in the DRAM, effectively placing some of the 169 // lower-order column bits as the least-significant bits 170 // of the address (above the ones denoting the burst size) 171 assert(columnsPerStripe >= 1); 172 173 // channel striping has to be done at a granularity that 174 // is equal or larger to a cache line 175 if (system()->cacheLineSize() > range.granularity()) { 176 fatal("Channel interleaving of %s must be at least as large " 177 "as the cache line size\n", name()); 178 } 179 180 // ...and equal or smaller than the row-buffer size 181 if (rowBufferSize < range.granularity()) { 182 fatal("Channel interleaving of %s must be at most as large " 183 "as the row-buffer size\n", name()); 184 } 185 // this is essentially the check above, so just to be sure 186 assert(columnsPerStripe <= columnsPerRowBuffer); 187 } 188 } 189 190 // some basic sanity checks 191 if (tREFI <= tRP || tREFI <= tRFC) { 192 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 193 tREFI, tRP, tRFC); 194 } 195 196 // basic bank group architecture checks -> 197 if (bankGroupArch) { 198 // must have at least one bank per bank group 199 if (bankGroupsPerRank > banksPerRank) { 200 fatal("banks per rank (%d) must be equal to or larger than " 201 "banks groups per rank (%d)\n", 202 banksPerRank, bankGroupsPerRank); 203 } 204 // must have same number of banks in each bank group 205 if ((banksPerRank % bankGroupsPerRank) != 0) { 206 fatal("Banks per rank (%d) must be evenly divisible by bank groups " 207 "per rank (%d) for equal banks per bank group\n", 208 banksPerRank, bankGroupsPerRank); 209 } 210 // tCCD_L should be greater than minimal, back-to-back burst delay 211 if (tCCD_L <= tBURST) { 212 fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 213 "bank groups per rank (%d) is greater than 1\n", 214 tCCD_L, tBURST, bankGroupsPerRank); 215 } 216 // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 217 // some datasheets might specify it equal to tRRD 218 if (tRRD_L < tRRD) { 219 fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 220 "bank groups per rank (%d) is greater than 1\n", 221 tRRD_L, tRRD, bankGroupsPerRank); 222 } 223 } 224 225} 226 227void 228DRAMCtrl::init() 229{ 230 AbstractMemory::init(); 231 232 if (!port.isConnected()) { 233 fatal("DRAMCtrl %s is unconnected!\n", name()); 234 } else { 235 port.sendRangeChange(); 236 } 237} 238 239void 240DRAMCtrl::startup() 241{
| 61 retryRdReq(false), retryWrReq(false), 62 busState(READ), 63 nextReqEvent(this), respondEvent(this), 64 drainManager(NULL), 65 deviceSize(p->device_size), 66 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 67 deviceRowBufferSize(p->device_rowbuffer_size), 68 devicesPerRank(p->devices_per_rank), 69 burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 70 rowBufferSize(devicesPerRank * deviceRowBufferSize), 71 columnsPerRowBuffer(rowBufferSize / burstSize), 72 columnsPerStripe(range.granularity() / burstSize), 73 ranksPerChannel(p->ranks_per_channel), 74 bankGroupsPerRank(p->bank_groups_per_rank), 75 bankGroupArch(p->bank_groups_per_rank > 0), 76 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 77 readBufferSize(p->read_buffer_size), 78 writeBufferSize(p->write_buffer_size), 79 writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 80 writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 81 minWritesPerSwitch(p->min_writes_per_switch), 82 writesThisTime(0), readsThisTime(0), 83 tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 84 tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 85 tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 86 tRRD_L(p->tRRD_L), tXAW(p->tXAW), activationLimit(p->activation_limit), 87 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 88 pageMgmt(p->page_policy), 89 maxAccessesPerRow(p->max_accesses_per_row), 90 frontendLatency(p->static_frontend_latency), 91 backendLatency(p->static_backend_latency), 92 busBusyUntil(0), prevArrival(0), 93 nextReqTime(0), activeRank(0), timeStampOffset(0) 94{ 95 for (int i = 0; i < ranksPerChannel; i++) { 96 Rank* rank = new Rank(*this, p); 97 ranks.push_back(rank); 98 99 rank->actTicks.resize(activationLimit, 0); 100 rank->banks.resize(banksPerRank); 101 rank->rank = i; 102 103 for (int b = 0; b < banksPerRank; b++) { 104 rank->banks[b].bank = b; 105 // GDDR addressing of banks to BG is linear. 106 // Here we assume that all DRAM generations address bank groups as 107 // follows: 108 if (bankGroupArch) { 109 // Simply assign lower bits to bank group in order to 110 // rotate across bank groups as banks are incremented 111 // e.g. with 4 banks per bank group and 16 banks total: 112 // banks 0,4,8,12 are in bank group 0 113 // banks 1,5,9,13 are in bank group 1 114 // banks 2,6,10,14 are in bank group 2 115 // banks 3,7,11,15 are in bank group 3 116 rank->banks[b].bankgr = b % bankGroupsPerRank; 117 } else { 118 // No bank groups; simply assign to bank number 119 rank->banks[b].bankgr = b; 120 } 121 } 122 } 123 124 // perform a basic check of the write thresholds 125 if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 126 fatal("Write buffer low threshold %d must be smaller than the " 127 "high threshold %d\n", p->write_low_thresh_perc, 128 p->write_high_thresh_perc); 129 130 // determine the rows per bank by looking at the total capacity 131 uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 132 133 // determine the dram actual capacity from the DRAM config in Mbytes 134 uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 135 ranksPerChannel; 136 137 // if actual DRAM size does not match memory capacity in system warn! 138 if (deviceCapacity != capacity / (1024 * 1024)) 139 warn("DRAM device capacity (%d Mbytes) does not match the " 140 "address range assigned (%d Mbytes)\n", deviceCapacity, 141 capacity / (1024 * 1024)); 142 143 DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 144 AbstractMemory::size()); 145 146 DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 147 rowBufferSize, columnsPerRowBuffer); 148 149 rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 150 151 // a bit of sanity checks on the interleaving 152 if (range.interleaved()) { 153 if (channels != range.stripes()) 154 fatal("%s has %d interleaved address stripes but %d channel(s)\n", 155 name(), range.stripes(), channels); 156 157 if (addrMapping == Enums::RoRaBaChCo) { 158 if (rowBufferSize != range.granularity()) { 159 fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 160 "address map\n", name()); 161 } 162 } else if (addrMapping == Enums::RoRaBaCoCh || 163 addrMapping == Enums::RoCoRaBaCh) { 164 // for the interleavings with channel bits in the bottom, 165 // if the system uses a channel striping granularity that 166 // is larger than the DRAM burst size, then map the 167 // sequential accesses within a stripe to a number of 168 // columns in the DRAM, effectively placing some of the 169 // lower-order column bits as the least-significant bits 170 // of the address (above the ones denoting the burst size) 171 assert(columnsPerStripe >= 1); 172 173 // channel striping has to be done at a granularity that 174 // is equal or larger to a cache line 175 if (system()->cacheLineSize() > range.granularity()) { 176 fatal("Channel interleaving of %s must be at least as large " 177 "as the cache line size\n", name()); 178 } 179 180 // ...and equal or smaller than the row-buffer size 181 if (rowBufferSize < range.granularity()) { 182 fatal("Channel interleaving of %s must be at most as large " 183 "as the row-buffer size\n", name()); 184 } 185 // this is essentially the check above, so just to be sure 186 assert(columnsPerStripe <= columnsPerRowBuffer); 187 } 188 } 189 190 // some basic sanity checks 191 if (tREFI <= tRP || tREFI <= tRFC) { 192 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 193 tREFI, tRP, tRFC); 194 } 195 196 // basic bank group architecture checks -> 197 if (bankGroupArch) { 198 // must have at least one bank per bank group 199 if (bankGroupsPerRank > banksPerRank) { 200 fatal("banks per rank (%d) must be equal to or larger than " 201 "banks groups per rank (%d)\n", 202 banksPerRank, bankGroupsPerRank); 203 } 204 // must have same number of banks in each bank group 205 if ((banksPerRank % bankGroupsPerRank) != 0) { 206 fatal("Banks per rank (%d) must be evenly divisible by bank groups " 207 "per rank (%d) for equal banks per bank group\n", 208 banksPerRank, bankGroupsPerRank); 209 } 210 // tCCD_L should be greater than minimal, back-to-back burst delay 211 if (tCCD_L <= tBURST) { 212 fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 213 "bank groups per rank (%d) is greater than 1\n", 214 tCCD_L, tBURST, bankGroupsPerRank); 215 } 216 // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 217 // some datasheets might specify it equal to tRRD 218 if (tRRD_L < tRRD) { 219 fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 220 "bank groups per rank (%d) is greater than 1\n", 221 tRRD_L, tRRD, bankGroupsPerRank); 222 } 223 } 224 225} 226 227void 228DRAMCtrl::init() 229{ 230 AbstractMemory::init(); 231 232 if (!port.isConnected()) { 233 fatal("DRAMCtrl %s is unconnected!\n", name()); 234 } else { 235 port.sendRangeChange(); 236 } 237} 238 239void 240DRAMCtrl::startup() 241{
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256} 257 258Tick 259DRAMCtrl::recvAtomic(PacketPtr pkt) 260{ 261 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 262 263 // do the actual memory access and turn the packet into a response 264 access(pkt); 265 266 Tick latency = 0; 267 if (!pkt->memInhibitAsserted() && pkt->hasData()) { 268 // this value is not supposed to be accurate, just enough to 269 // keep things going, mimic a closed page 270 latency = tRP + tRCD + tCL; 271 } 272 return latency; 273} 274 275bool 276DRAMCtrl::readQueueFull(unsigned int neededEntries) const 277{ 278 DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 279 readBufferSize, readQueue.size() + respQueue.size(), 280 neededEntries); 281 282 return 283 (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 284} 285 286bool 287DRAMCtrl::writeQueueFull(unsigned int neededEntries) const 288{ 289 DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 290 writeBufferSize, writeQueue.size(), neededEntries); 291 return (writeQueue.size() + neededEntries) > writeBufferSize; 292} 293 294DRAMCtrl::DRAMPacket* 295DRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 296 bool isRead) 297{ 298 // decode the address based on the address mapping scheme, with 299 // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 300 // channel, respectively 301 uint8_t rank; 302 uint8_t bank; 303 // use a 64-bit unsigned during the computations as the row is 304 // always the top bits, and check before creating the DRAMPacket 305 uint64_t row; 306 307 // truncate the address to a DRAM burst, which makes it unique to 308 // a specific column, row, bank, rank and channel 309 Addr addr = dramPktAddr / burstSize; 310 311 // we have removed the lowest order address bits that denote the 312 // position within the column 313 if (addrMapping == Enums::RoRaBaChCo) { 314 // the lowest order bits denote the column to ensure that 315 // sequential cache lines occupy the same row 316 addr = addr / columnsPerRowBuffer; 317 318 // take out the channel part of the address 319 addr = addr / channels; 320 321 // after the channel bits, get the bank bits to interleave 322 // over the banks 323 bank = addr % banksPerRank; 324 addr = addr / banksPerRank; 325 326 // after the bank, we get the rank bits which thus interleaves 327 // over the ranks 328 rank = addr % ranksPerChannel; 329 addr = addr / ranksPerChannel; 330 331 // lastly, get the row bits 332 row = addr % rowsPerBank; 333 addr = addr / rowsPerBank; 334 } else if (addrMapping == Enums::RoRaBaCoCh) { 335 // take out the lower-order column bits 336 addr = addr / columnsPerStripe; 337 338 // take out the channel part of the address 339 addr = addr / channels; 340 341 // next, the higher-order column bites 342 addr = addr / (columnsPerRowBuffer / columnsPerStripe); 343 344 // after the column bits, we get the bank bits to interleave 345 // over the banks 346 bank = addr % banksPerRank; 347 addr = addr / banksPerRank; 348 349 // after the bank, we get the rank bits which thus interleaves 350 // over the ranks 351 rank = addr % ranksPerChannel; 352 addr = addr / ranksPerChannel; 353 354 // lastly, get the row bits 355 row = addr % rowsPerBank; 356 addr = addr / rowsPerBank; 357 } else if (addrMapping == Enums::RoCoRaBaCh) { 358 // optimise for closed page mode and utilise maximum 359 // parallelism of the DRAM (at the cost of power) 360 361 // take out the lower-order column bits 362 addr = addr / columnsPerStripe; 363 364 // take out the channel part of the address, not that this has 365 // to match with how accesses are interleaved between the 366 // controllers in the address mapping 367 addr = addr / channels; 368 369 // start with the bank bits, as this provides the maximum 370 // opportunity for parallelism between requests 371 bank = addr % banksPerRank; 372 addr = addr / banksPerRank; 373 374 // next get the rank bits 375 rank = addr % ranksPerChannel; 376 addr = addr / ranksPerChannel; 377 378 // next, the higher-order column bites 379 addr = addr / (columnsPerRowBuffer / columnsPerStripe); 380 381 // lastly, get the row bits 382 row = addr % rowsPerBank; 383 addr = addr / rowsPerBank; 384 } else 385 panic("Unknown address mapping policy chosen!"); 386 387 assert(rank < ranksPerChannel); 388 assert(bank < banksPerRank); 389 assert(row < rowsPerBank); 390 assert(row < Bank::NO_ROW); 391 392 DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 393 dramPktAddr, rank, bank, row); 394 395 // create the corresponding DRAM packet with the entry time and 396 // ready time set to the current tick, the latter will be updated 397 // later 398 uint16_t bank_id = banksPerRank * rank + bank; 399 return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 400 size, ranks[rank]->banks[bank], *ranks[rank]); 401} 402 403void 404DRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 405{ 406 // only add to the read queue here. whenever the request is 407 // eventually done, set the readyTime, and call schedule() 408 assert(!pkt->isWrite()); 409 410 assert(pktCount != 0); 411 412 // if the request size is larger than burst size, the pkt is split into 413 // multiple DRAM packets 414 // Note if the pkt starting address is not aligened to burst size, the 415 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 416 // are aligned to burst size boundaries. This is to ensure we accurately 417 // check read packets against packets in write queue. 418 Addr addr = pkt->getAddr(); 419 unsigned pktsServicedByWrQ = 0; 420 BurstHelper* burst_helper = NULL; 421 for (int cnt = 0; cnt < pktCount; ++cnt) { 422 unsigned size = std::min((addr | (burstSize - 1)) + 1, 423 pkt->getAddr() + pkt->getSize()) - addr; 424 readPktSize[ceilLog2(size)]++; 425 readBursts++; 426 427 // First check write buffer to see if the data is already at 428 // the controller 429 bool foundInWrQ = false; 430 for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 431 // check if the read is subsumed in the write entry we are 432 // looking at 433 if ((*i)->addr <= addr && 434 (addr + size) <= ((*i)->addr + (*i)->size)) { 435 foundInWrQ = true; 436 servicedByWrQ++; 437 pktsServicedByWrQ++; 438 DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 439 "write queue\n", addr, size); 440 bytesReadWrQ += burstSize; 441 break; 442 } 443 } 444 445 // If not found in the write q, make a DRAM packet and 446 // push it onto the read queue 447 if (!foundInWrQ) { 448 449 // Make the burst helper for split packets 450 if (pktCount > 1 && burst_helper == NULL) { 451 DPRINTF(DRAM, "Read to addr %lld translates to %d " 452 "dram requests\n", pkt->getAddr(), pktCount); 453 burst_helper = new BurstHelper(pktCount); 454 } 455 456 DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 457 dram_pkt->burstHelper = burst_helper; 458 459 assert(!readQueueFull(1)); 460 rdQLenPdf[readQueue.size() + respQueue.size()]++; 461 462 DPRINTF(DRAM, "Adding to read queue\n"); 463 464 readQueue.push_back(dram_pkt); 465 466 // Update stats 467 avgRdQLen = readQueue.size() + respQueue.size(); 468 } 469 470 // Starting address of next dram pkt (aligend to burstSize boundary) 471 addr = (addr | (burstSize - 1)) + 1; 472 } 473 474 // If all packets are serviced by write queue, we send the repsonse back 475 if (pktsServicedByWrQ == pktCount) { 476 accessAndRespond(pkt, frontendLatency); 477 return; 478 } 479 480 // Update how many split packets are serviced by write queue 481 if (burst_helper != NULL) 482 burst_helper->burstsServiced = pktsServicedByWrQ; 483 484 // If we are not already scheduled to get a request out of the 485 // queue, do so now 486 if (!nextReqEvent.scheduled()) { 487 DPRINTF(DRAM, "Request scheduled immediately\n"); 488 schedule(nextReqEvent, curTick()); 489 } 490} 491 492void 493DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 494{ 495 // only add to the write queue here. whenever the request is 496 // eventually done, set the readyTime, and call schedule() 497 assert(pkt->isWrite()); 498 499 // if the request size is larger than burst size, the pkt is split into 500 // multiple DRAM packets 501 Addr addr = pkt->getAddr(); 502 for (int cnt = 0; cnt < pktCount; ++cnt) { 503 unsigned size = std::min((addr | (burstSize - 1)) + 1, 504 pkt->getAddr() + pkt->getSize()) - addr; 505 writePktSize[ceilLog2(size)]++; 506 writeBursts++; 507 508 // see if we can merge with an existing item in the write 509 // queue and keep track of whether we have merged or not so we 510 // can stop at that point and also avoid enqueueing a new 511 // request 512 bool merged = false; 513 auto w = writeQueue.begin(); 514 515 while(!merged && w != writeQueue.end()) { 516 // either of the two could be first, if they are the same 517 // it does not matter which way we go 518 if ((*w)->addr >= addr) { 519 // the existing one starts after the new one, figure 520 // out where the new one ends with respect to the 521 // existing one 522 if ((addr + size) >= ((*w)->addr + (*w)->size)) { 523 // check if the existing one is completely 524 // subsumed in the new one 525 DPRINTF(DRAM, "Merging write covering existing burst\n"); 526 merged = true; 527 // update both the address and the size 528 (*w)->addr = addr; 529 (*w)->size = size; 530 } else if ((addr + size) >= (*w)->addr && 531 ((*w)->addr + (*w)->size - addr) <= burstSize) { 532 // the new one is just before or partially 533 // overlapping with the existing one, and together 534 // they fit within a burst 535 DPRINTF(DRAM, "Merging write before existing burst\n"); 536 merged = true; 537 // the existing queue item needs to be adjusted with 538 // respect to both address and size 539 (*w)->size = (*w)->addr + (*w)->size - addr; 540 (*w)->addr = addr; 541 } 542 } else { 543 // the new one starts after the current one, figure 544 // out where the existing one ends with respect to the 545 // new one 546 if (((*w)->addr + (*w)->size) >= (addr + size)) { 547 // check if the new one is completely subsumed in the 548 // existing one 549 DPRINTF(DRAM, "Merging write into existing burst\n"); 550 merged = true; 551 // no adjustments necessary 552 } else if (((*w)->addr + (*w)->size) >= addr && 553 (addr + size - (*w)->addr) <= burstSize) { 554 // the existing one is just before or partially 555 // overlapping with the new one, and together 556 // they fit within a burst 557 DPRINTF(DRAM, "Merging write after existing burst\n"); 558 merged = true; 559 // the address is right, and only the size has 560 // to be adjusted 561 (*w)->size = addr + size - (*w)->addr; 562 } 563 } 564 ++w; 565 } 566 567 // if the item was not merged we need to create a new write 568 // and enqueue it 569 if (!merged) { 570 DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 571 572 assert(writeQueue.size() < writeBufferSize); 573 wrQLenPdf[writeQueue.size()]++; 574 575 DPRINTF(DRAM, "Adding to write queue\n"); 576 577 writeQueue.push_back(dram_pkt); 578 579 // Update stats 580 avgWrQLen = writeQueue.size(); 581 } else { 582 // keep track of the fact that this burst effectively 583 // disappeared as it was merged with an existing one 584 mergedWrBursts++; 585 } 586 587 // Starting address of next dram pkt (aligend to burstSize boundary) 588 addr = (addr | (burstSize - 1)) + 1; 589 } 590 591 // we do not wait for the writes to be send to the actual memory, 592 // but instead take responsibility for the consistency here and 593 // snoop the write queue for any upcoming reads 594 // @todo, if a pkt size is larger than burst size, we might need a 595 // different front end latency 596 accessAndRespond(pkt, frontendLatency); 597 598 // If we are not already scheduled to get a request out of the 599 // queue, do so now 600 if (!nextReqEvent.scheduled()) { 601 DPRINTF(DRAM, "Request scheduled immediately\n"); 602 schedule(nextReqEvent, curTick()); 603 } 604} 605 606void 607DRAMCtrl::printQs() const { 608 DPRINTF(DRAM, "===READ QUEUE===\n\n"); 609 for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 610 DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 611 } 612 DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 613 for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 614 DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 615 } 616 DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 617 for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 618 DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 619 } 620} 621 622bool 623DRAMCtrl::recvTimingReq(PacketPtr pkt) 624{ 625 /// @todo temporary hack to deal with memory corruption issues until 626 /// 4-phase transactions are complete 627 for (int x = 0; x < pendingDelete.size(); x++) 628 delete pendingDelete[x]; 629 pendingDelete.clear(); 630 631 // This is where we enter from the outside world 632 DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 633 pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 634 635 // simply drop inhibited packets for now 636 if (pkt->memInhibitAsserted()) { 637 DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 638 pendingDelete.push_back(pkt); 639 return true; 640 } 641 642 // Calc avg gap between requests 643 if (prevArrival != 0) { 644 totGap += curTick() - prevArrival; 645 } 646 prevArrival = curTick(); 647 648 649 // Find out how many dram packets a pkt translates to 650 // If the burst size is equal or larger than the pkt size, then a pkt 651 // translates to only one dram packet. Otherwise, a pkt translates to 652 // multiple dram packets 653 unsigned size = pkt->getSize(); 654 unsigned offset = pkt->getAddr() & (burstSize - 1); 655 unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 656 657 // check local buffers and do not accept if full 658 if (pkt->isRead()) { 659 assert(size != 0); 660 if (readQueueFull(dram_pkt_count)) { 661 DPRINTF(DRAM, "Read queue full, not accepting\n"); 662 // remember that we have to retry this port 663 retryRdReq = true; 664 numRdRetry++; 665 return false; 666 } else { 667 addToReadQueue(pkt, dram_pkt_count); 668 readReqs++; 669 bytesReadSys += size; 670 } 671 } else if (pkt->isWrite()) { 672 assert(size != 0); 673 if (writeQueueFull(dram_pkt_count)) { 674 DPRINTF(DRAM, "Write queue full, not accepting\n"); 675 // remember that we have to retry this port 676 retryWrReq = true; 677 numWrRetry++; 678 return false; 679 } else { 680 addToWriteQueue(pkt, dram_pkt_count); 681 writeReqs++; 682 bytesWrittenSys += size; 683 } 684 } else { 685 DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 686 neitherReadNorWrite++; 687 accessAndRespond(pkt, 1); 688 } 689 690 return true; 691} 692 693void 694DRAMCtrl::processRespondEvent() 695{ 696 DPRINTF(DRAM, 697 "processRespondEvent(): Some req has reached its readyTime\n"); 698 699 DRAMPacket* dram_pkt = respQueue.front(); 700 701 if (dram_pkt->burstHelper) { 702 // it is a split packet 703 dram_pkt->burstHelper->burstsServiced++; 704 if (dram_pkt->burstHelper->burstsServiced == 705 dram_pkt->burstHelper->burstCount) { 706 // we have now serviced all children packets of a system packet 707 // so we can now respond to the requester 708 // @todo we probably want to have a different front end and back 709 // end latency for split packets 710 accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 711 delete dram_pkt->burstHelper; 712 dram_pkt->burstHelper = NULL; 713 } 714 } else { 715 // it is not a split packet 716 accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 717 } 718 719 delete respQueue.front(); 720 respQueue.pop_front(); 721 722 if (!respQueue.empty()) { 723 assert(respQueue.front()->readyTime >= curTick()); 724 assert(!respondEvent.scheduled()); 725 schedule(respondEvent, respQueue.front()->readyTime); 726 } else { 727 // if there is nothing left in any queue, signal a drain 728 if (writeQueue.empty() && readQueue.empty() && 729 drainManager) { 730 DPRINTF(Drain, "DRAM controller done draining\n"); 731 drainManager->signalDrainDone(); 732 drainManager = NULL; 733 } 734 } 735 736 // We have made a location in the queue available at this point, 737 // so if there is a read that was forced to wait, retry now 738 if (retryRdReq) { 739 retryRdReq = false; 740 port.sendRetry(); 741 } 742} 743 744bool 745DRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 746{ 747 // This method does the arbitration between requests. The chosen 748 // packet is simply moved to the head of the queue. The other 749 // methods know that this is the place to look. For example, with 750 // FCFS, this method does nothing 751 assert(!queue.empty()); 752 753 // bool to indicate if a packet to an available rank is found 754 bool found_packet = false; 755 if (queue.size() == 1) { 756 DRAMPacket* dram_pkt = queue.front(); 757 // available rank corresponds to state refresh idle 758 if (ranks[dram_pkt->rank]->isAvailable()) { 759 found_packet = true; 760 DPRINTF(DRAM, "Single request, going to a free rank\n"); 761 } else { 762 DPRINTF(DRAM, "Single request, going to a busy rank\n"); 763 } 764 return found_packet; 765 } 766 767 if (memSchedPolicy == Enums::fcfs) { 768 // check if there is a packet going to a free rank 769 for(auto i = queue.begin(); i != queue.end() ; ++i) { 770 DRAMPacket* dram_pkt = *i; 771 if (ranks[dram_pkt->rank]->isAvailable()) { 772 queue.erase(i); 773 queue.push_front(dram_pkt); 774 found_packet = true; 775 break; 776 } 777 } 778 } else if (memSchedPolicy == Enums::frfcfs) { 779 found_packet = reorderQueue(queue, switched_cmd_type); 780 } else 781 panic("No scheduling policy chosen\n"); 782 return found_packet; 783} 784 785bool 786DRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 787{ 788 // Only determine this when needed 789 uint64_t earliest_banks = 0; 790 791 // Search for row hits first, if no row hit is found then schedule the 792 // packet to one of the earliest banks available 793 bool found_packet = false; 794 bool found_earliest_pkt = false; 795 bool found_prepped_diff_rank_pkt = false; 796 auto selected_pkt_it = queue.end(); 797 798 for (auto i = queue.begin(); i != queue.end() ; ++i) { 799 DRAMPacket* dram_pkt = *i; 800 const Bank& bank = dram_pkt->bankRef; 801 // check if rank is busy. If this is the case jump to the next packet 802 // Check if it is a row hit 803 if (dram_pkt->rankRef.isAvailable()) { 804 if (bank.openRow == dram_pkt->row) { 805 if (dram_pkt->rank == activeRank || switched_cmd_type) { 806 // FCFS within the hits, giving priority to commands 807 // that access the same rank as the previous burst 808 // to minimize bus turnaround delays 809 // Only give rank prioity when command type is 810 // not changing 811 DPRINTF(DRAM, "Row buffer hit\n"); 812 selected_pkt_it = i; 813 break; 814 } else if (!found_prepped_diff_rank_pkt) { 815 // found row hit for command on different rank 816 // than prev burst 817 selected_pkt_it = i; 818 found_prepped_diff_rank_pkt = true; 819 } 820 } else if (!found_earliest_pkt & !found_prepped_diff_rank_pkt) { 821 // packet going to a rank which is currently not waiting for a 822 // refresh, No row hit and 823 // haven't found an entry with a row hit to a new rank 824 if (earliest_banks == 0) 825 // Determine entries with earliest bank prep delay 826 // Function will give priority to commands that access the 827 // same rank as previous burst and can prep 828 // the bank seamlessly 829 earliest_banks = minBankPrep(queue, switched_cmd_type); 830 831 // FCFS - Bank is first available bank 832 if (bits(earliest_banks, dram_pkt->bankId, 833 dram_pkt->bankId)) { 834 // Remember the packet to be scheduled to one of 835 // the earliest banks available, FCFS amongst the 836 // earliest banks 837 selected_pkt_it = i; 838 //if the packet found is going to a rank that is currently 839 //not busy then update the found_packet to true 840 found_earliest_pkt = true; 841 } 842 } 843 } 844 } 845 846 if (selected_pkt_it != queue.end()) { 847 DRAMPacket* selected_pkt = *selected_pkt_it; 848 queue.erase(selected_pkt_it); 849 queue.push_front(selected_pkt); 850 found_packet = true; 851 } 852 return found_packet; 853} 854 855void 856DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 857{ 858 DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 859 860 bool needsResponse = pkt->needsResponse(); 861 // do the actual memory access which also turns the packet into a 862 // response 863 access(pkt); 864 865 // turn packet around to go back to requester if response expected 866 if (needsResponse) { 867 // access already turned the packet into a response 868 assert(pkt->isResponse()); 869 870 // @todo someone should pay for this 871 pkt->firstWordDelay = pkt->lastWordDelay = 0; 872 873 // queue the packet in the response queue to be sent out after 874 // the static latency has passed 875 port.schedTimingResp(pkt, curTick() + static_latency); 876 } else { 877 // @todo the packet is going to be deleted, and the DRAMPacket 878 // is still having a pointer to it 879 pendingDelete.push_back(pkt); 880 } 881 882 DPRINTF(DRAM, "Done\n"); 883 884 return; 885} 886 887void 888DRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 889 Tick act_tick, uint32_t row) 890{ 891 assert(rank_ref.actTicks.size() == activationLimit); 892 893 DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 894 895 // update the open row 896 assert(bank_ref.openRow == Bank::NO_ROW); 897 bank_ref.openRow = row; 898 899 // start counting anew, this covers both the case when we 900 // auto-precharged, and when this access is forced to 901 // precharge 902 bank_ref.bytesAccessed = 0; 903 bank_ref.rowAccesses = 0; 904 905 ++rank_ref.numBanksActive; 906 assert(rank_ref.numBanksActive <= banksPerRank); 907 908 DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 909 bank_ref.bank, rank_ref.rank, act_tick, 910 ranks[rank_ref.rank]->numBanksActive); 911 912 rank_ref.power.powerlib.doCommand(MemCommand::ACT, bank_ref.bank, 913 divCeil(act_tick, tCK) - 914 timeStampOffset); 915 916 DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 917 timeStampOffset, bank_ref.bank, rank_ref.rank); 918 919 // The next access has to respect tRAS for this bank 920 bank_ref.preAllowedAt = act_tick + tRAS; 921 922 // Respect the row-to-column command delay 923 bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt); 924 925 // start by enforcing tRRD 926 for(int i = 0; i < banksPerRank; i++) { 927 // next activate to any bank in this rank must not happen 928 // before tRRD 929 if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 930 // bank group architecture requires longer delays between 931 // ACT commands within the same bank group. Use tRRD_L 932 // in this case 933 rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 934 rank_ref.banks[i].actAllowedAt); 935 } else { 936 // use shorter tRRD value when either 937 // 1) bank group architecture is not supportted 938 // 2) bank is in a different bank group 939 rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 940 rank_ref.banks[i].actAllowedAt); 941 } 942 } 943 944 // next, we deal with tXAW, if the activation limit is disabled 945 // then we directly schedule an activate power event 946 if (!rank_ref.actTicks.empty()) { 947 // sanity check 948 if (rank_ref.actTicks.back() && 949 (act_tick - rank_ref.actTicks.back()) < tXAW) { 950 panic("Got %d activates in window %d (%llu - %llu) which " 951 "is smaller than %llu\n", activationLimit, act_tick - 952 rank_ref.actTicks.back(), act_tick, 953 rank_ref.actTicks.back(), tXAW); 954 } 955 956 // shift the times used for the book keeping, the last element 957 // (highest index) is the oldest one and hence the lowest value 958 rank_ref.actTicks.pop_back(); 959 960 // record an new activation (in the future) 961 rank_ref.actTicks.push_front(act_tick); 962 963 // cannot activate more than X times in time window tXAW, push the 964 // next one (the X + 1'st activate) to be tXAW away from the 965 // oldest in our window of X 966 if (rank_ref.actTicks.back() && 967 (act_tick - rank_ref.actTicks.back()) < tXAW) { 968 DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 969 "no earlier than %llu\n", activationLimit, 970 rank_ref.actTicks.back() + tXAW); 971 for(int j = 0; j < banksPerRank; j++) 972 // next activate must not happen before end of window 973 rank_ref.banks[j].actAllowedAt = 974 std::max(rank_ref.actTicks.back() + tXAW, 975 rank_ref.banks[j].actAllowedAt); 976 } 977 } 978 979 // at the point when this activate takes place, make sure we 980 // transition to the active power state 981 if (!rank_ref.activateEvent.scheduled()) 982 schedule(rank_ref.activateEvent, act_tick); 983 else if (rank_ref.activateEvent.when() > act_tick) 984 // move it sooner in time 985 reschedule(rank_ref.activateEvent, act_tick); 986} 987 988void 989DRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 990{ 991 // make sure the bank has an open row 992 assert(bank.openRow != Bank::NO_ROW); 993 994 // sample the bytes per activate here since we are closing 995 // the page 996 bytesPerActivate.sample(bank.bytesAccessed); 997 998 bank.openRow = Bank::NO_ROW; 999 1000 // no precharge allowed before this one 1001 bank.preAllowedAt = pre_at; 1002 1003 Tick pre_done_at = pre_at + tRP; 1004 1005 bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 1006 1007 assert(rank_ref.numBanksActive != 0); 1008 --rank_ref.numBanksActive; 1009 1010 DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 1011 "%d active\n", bank.bank, rank_ref.rank, pre_at, 1012 rank_ref.numBanksActive); 1013 1014 if (trace) { 1015 1016 rank_ref.power.powerlib.doCommand(MemCommand::PRE, bank.bank, 1017 divCeil(pre_at, tCK) - 1018 timeStampOffset); 1019 DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 1020 timeStampOffset, bank.bank, rank_ref.rank); 1021 } 1022 // if we look at the current number of active banks we might be 1023 // tempted to think the DRAM is now idle, however this can be 1024 // undone by an activate that is scheduled to happen before we 1025 // would have reached the idle state, so schedule an event and 1026 // rather check once we actually make it to the point in time when 1027 // the (last) precharge takes place 1028 if (!rank_ref.prechargeEvent.scheduled()) 1029 schedule(rank_ref.prechargeEvent, pre_done_at); 1030 else if (rank_ref.prechargeEvent.when() < pre_done_at) 1031 reschedule(rank_ref.prechargeEvent, pre_done_at); 1032} 1033 1034void 1035DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 1036{ 1037 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 1038 dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 1039 1040 // get the rank 1041 Rank& rank = dram_pkt->rankRef; 1042 1043 // get the bank 1044 Bank& bank = dram_pkt->bankRef; 1045 1046 // for the state we need to track if it is a row hit or not 1047 bool row_hit = true; 1048 1049 // respect any constraints on the command (e.g. tRCD or tCCD) 1050 Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 1051 1052 // Determine the access latency and update the bank state 1053 if (bank.openRow == dram_pkt->row) { 1054 // nothing to do 1055 } else { 1056 row_hit = false; 1057 1058 // If there is a page open, precharge it. 1059 if (bank.openRow != Bank::NO_ROW) { 1060 prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 1061 } 1062 1063 // next we need to account for the delay in activating the 1064 // page 1065 Tick act_tick = std::max(bank.actAllowedAt, curTick()); 1066 1067 // Record the activation and deal with all the global timing 1068 // constraints caused be a new activation (tRRD and tXAW) 1069 activateBank(rank, bank, act_tick, dram_pkt->row); 1070 1071 // issue the command as early as possible 1072 cmd_at = bank.colAllowedAt; 1073 } 1074 1075 // we need to wait until the bus is available before we can issue 1076 // the command 1077 cmd_at = std::max(cmd_at, busBusyUntil - tCL); 1078 1079 // update the packet ready time 1080 dram_pkt->readyTime = cmd_at + tCL + tBURST; 1081 1082 // only one burst can use the bus at any one point in time 1083 assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 1084 1085 // update the time for the next read/write burst for each 1086 // bank (add a max with tCCD/tCCD_L here) 1087 Tick cmd_dly; 1088 for(int j = 0; j < ranksPerChannel; j++) { 1089 for(int i = 0; i < banksPerRank; i++) { 1090 // next burst to same bank group in this rank must not happen 1091 // before tCCD_L. Different bank group timing requirement is 1092 // tBURST; Add tCS for different ranks 1093 if (dram_pkt->rank == j) { 1094 if (bankGroupArch && 1095 (bank.bankgr == ranks[j]->banks[i].bankgr)) { 1096 // bank group architecture requires longer delays between 1097 // RD/WR burst commands to the same bank group. 1098 // Use tCCD_L in this case 1099 cmd_dly = tCCD_L; 1100 } else { 1101 // use tBURST (equivalent to tCCD_S), the shorter 1102 // cas-to-cas delay value, when either: 1103 // 1) bank group architecture is not supportted 1104 // 2) bank is in a different bank group 1105 cmd_dly = tBURST; 1106 } 1107 } else { 1108 // different rank is by default in a different bank group 1109 // use tBURST (equivalent to tCCD_S), which is the shorter 1110 // cas-to-cas delay in this case 1111 // Add tCS to account for rank-to-rank bus delay requirements 1112 cmd_dly = tBURST + tCS; 1113 } 1114 ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly, 1115 ranks[j]->banks[i].colAllowedAt); 1116 } 1117 } 1118 1119 // Save rank of current access 1120 activeRank = dram_pkt->rank; 1121 1122 // If this is a write, we also need to respect the write recovery 1123 // time before a precharge, in the case of a read, respect the 1124 // read to precharge constraint 1125 bank.preAllowedAt = std::max(bank.preAllowedAt, 1126 dram_pkt->isRead ? cmd_at + tRTP : 1127 dram_pkt->readyTime + tWR); 1128 1129 // increment the bytes accessed and the accesses per row 1130 bank.bytesAccessed += burstSize; 1131 ++bank.rowAccesses; 1132 1133 // if we reached the max, then issue with an auto-precharge 1134 bool auto_precharge = pageMgmt == Enums::close || 1135 bank.rowAccesses == maxAccessesPerRow; 1136 1137 // if we did not hit the limit, we might still want to 1138 // auto-precharge 1139 if (!auto_precharge && 1140 (pageMgmt == Enums::open_adaptive || 1141 pageMgmt == Enums::close_adaptive)) { 1142 // a twist on the open and close page policies: 1143 // 1) open_adaptive page policy does not blindly keep the 1144 // page open, but close it if there are no row hits, and there 1145 // are bank conflicts in the queue 1146 // 2) close_adaptive page policy does not blindly close the 1147 // page, but closes it only if there are no row hits in the queue. 1148 // In this case, only force an auto precharge when there 1149 // are no same page hits in the queue 1150 bool got_more_hits = false; 1151 bool got_bank_conflict = false; 1152 1153 // either look at the read queue or write queue 1154 const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 1155 writeQueue; 1156 auto p = queue.begin(); 1157 // make sure we are not considering the packet that we are 1158 // currently dealing with (which is the head of the queue) 1159 ++p; 1160 1161 // keep on looking until we have found required condition or 1162 // reached the end 1163 while (!(got_more_hits && 1164 (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 1165 p != queue.end()) { 1166 bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 1167 (dram_pkt->bank == (*p)->bank); 1168 bool same_row = dram_pkt->row == (*p)->row; 1169 got_more_hits |= same_rank_bank && same_row; 1170 got_bank_conflict |= same_rank_bank && !same_row; 1171 ++p; 1172 } 1173 1174 // auto pre-charge when either 1175 // 1) open_adaptive policy, we have not got any more hits, and 1176 // have a bank conflict 1177 // 2) close_adaptive policy and we have not got any more hits 1178 auto_precharge = !got_more_hits && 1179 (got_bank_conflict || pageMgmt == Enums::close_adaptive); 1180 } 1181 1182 // DRAMPower trace command to be written 1183 std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 1184 1185 // MemCommand required for DRAMPower library 1186 MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 1187 MemCommand::WR; 1188 1189 // if this access should use auto-precharge, then we are 1190 // closing the row 1191 if (auto_precharge) { 1192 // if auto-precharge push a PRE command at the correct tick to the 1193 // list used by DRAMPower library to calculate power 1194 prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 1195 1196 DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 1197 } 1198 1199 // Update bus state 1200 busBusyUntil = dram_pkt->readyTime; 1201 1202 DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 1203 dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 1204 1205 dram_pkt->rankRef.power.powerlib.doCommand(command, dram_pkt->bank, 1206 divCeil(cmd_at, tCK) - 1207 timeStampOffset); 1208 1209 DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 1210 timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 1211 1212 // Update the minimum timing between the requests, this is a 1213 // conservative estimate of when we have to schedule the next 1214 // request to not introduce any unecessary bubbles. In most cases 1215 // we will wake up sooner than we have to. 1216 nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 1217 1218 // Update the stats and schedule the next request 1219 if (dram_pkt->isRead) { 1220 ++readsThisTime; 1221 if (row_hit) 1222 readRowHits++; 1223 bytesReadDRAM += burstSize; 1224 perBankRdBursts[dram_pkt->bankId]++; 1225 1226 // Update latency stats 1227 totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 1228 totBusLat += tBURST; 1229 totQLat += cmd_at - dram_pkt->entryTime; 1230 } else { 1231 ++writesThisTime; 1232 if (row_hit) 1233 writeRowHits++; 1234 bytesWritten += burstSize; 1235 perBankWrBursts[dram_pkt->bankId]++; 1236 } 1237} 1238 1239void 1240DRAMCtrl::processNextReqEvent() 1241{ 1242 int busyRanks = 0; 1243 for (auto r : ranks) { 1244 if (!r->isAvailable()) { 1245 // rank is busy refreshing 1246 busyRanks++; 1247 1248 // let the rank know that if it was waiting to drain, it 1249 // is now done and ready to proceed 1250 r->checkDrainDone(); 1251 } 1252 } 1253 1254 if (busyRanks == ranksPerChannel) { 1255 // if all ranks are refreshing wait for them to finish 1256 // and stall this state machine without taking any further 1257 // action, and do not schedule a new nextReqEvent 1258 return; 1259 } 1260 1261 // pre-emptively set to false. Overwrite if in READ_TO_WRITE 1262 // or WRITE_TO_READ state 1263 bool switched_cmd_type = false; 1264 if (busState == READ_TO_WRITE) { 1265 DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 1266 "waiting\n", readsThisTime, readQueue.size()); 1267 1268 // sample and reset the read-related stats as we are now 1269 // transitioning to writes, and all reads are done 1270 rdPerTurnAround.sample(readsThisTime); 1271 readsThisTime = 0; 1272 1273 // now proceed to do the actual writes 1274 busState = WRITE; 1275 switched_cmd_type = true; 1276 } else if (busState == WRITE_TO_READ) { 1277 DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 1278 "waiting\n", writesThisTime, writeQueue.size()); 1279 1280 wrPerTurnAround.sample(writesThisTime); 1281 writesThisTime = 0; 1282 1283 busState = READ; 1284 switched_cmd_type = true; 1285 } 1286 1287 // when we get here it is either a read or a write 1288 if (busState == READ) { 1289 1290 // track if we should switch or not 1291 bool switch_to_writes = false; 1292 1293 if (readQueue.empty()) { 1294 // In the case there is no read request to go next, 1295 // trigger writes if we have passed the low threshold (or 1296 // if we are draining) 1297 if (!writeQueue.empty() && 1298 (drainManager || writeQueue.size() > writeLowThreshold)) { 1299 1300 switch_to_writes = true; 1301 } else { 1302 // check if we are drained 1303 if (respQueue.empty () && drainManager) { 1304 DPRINTF(Drain, "DRAM controller done draining\n"); 1305 drainManager->signalDrainDone(); 1306 drainManager = NULL; 1307 } 1308 1309 // nothing to do, not even any point in scheduling an 1310 // event for the next request 1311 return; 1312 } 1313 } else { 1314 // bool to check if there is a read to a free rank 1315 bool found_read = false; 1316 1317 // Figure out which read request goes next, and move it to the 1318 // front of the read queue 1319 found_read = chooseNext(readQueue, switched_cmd_type); 1320 1321 // if no read to an available rank is found then return 1322 // at this point. There could be writes to the available ranks 1323 // which are above the required threshold. However, to 1324 // avoid adding more complexity to the code, return and wait 1325 // for a refresh event to kick things into action again. 1326 if (!found_read) 1327 return; 1328 1329 DRAMPacket* dram_pkt = readQueue.front(); 1330 assert(dram_pkt->rankRef.isAvailable()); 1331 // here we get a bit creative and shift the bus busy time not 1332 // just the tWTR, but also a CAS latency to capture the fact 1333 // that we are allowed to prepare a new bank, but not issue a 1334 // read command until after tWTR, in essence we capture a 1335 // bubble on the data bus that is tWTR + tCL 1336 if (switched_cmd_type && dram_pkt->rank == activeRank) { 1337 busBusyUntil += tWTR + tCL; 1338 } 1339 1340 doDRAMAccess(dram_pkt); 1341 1342 // At this point we're done dealing with the request 1343 readQueue.pop_front(); 1344 1345 // sanity check 1346 assert(dram_pkt->size <= burstSize); 1347 assert(dram_pkt->readyTime >= curTick()); 1348 1349 // Insert into response queue. It will be sent back to the 1350 // requestor at its readyTime 1351 if (respQueue.empty()) { 1352 assert(!respondEvent.scheduled()); 1353 schedule(respondEvent, dram_pkt->readyTime); 1354 } else { 1355 assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 1356 assert(respondEvent.scheduled()); 1357 } 1358 1359 respQueue.push_back(dram_pkt); 1360 1361 // we have so many writes that we have to transition 1362 if (writeQueue.size() > writeHighThreshold) { 1363 switch_to_writes = true; 1364 } 1365 } 1366 1367 // switching to writes, either because the read queue is empty 1368 // and the writes have passed the low threshold (or we are 1369 // draining), or because the writes hit the hight threshold 1370 if (switch_to_writes) { 1371 // transition to writing 1372 busState = READ_TO_WRITE; 1373 } 1374 } else { 1375 // bool to check if write to free rank is found 1376 bool found_write = false; 1377 1378 found_write = chooseNext(writeQueue, switched_cmd_type); 1379 1380 // if no writes to an available rank are found then return. 1381 // There could be reads to the available ranks. However, to avoid 1382 // adding more complexity to the code, return at this point and wait 1383 // for a refresh event to kick things into action again. 1384 if (!found_write) 1385 return; 1386 1387 DRAMPacket* dram_pkt = writeQueue.front(); 1388 assert(dram_pkt->rankRef.isAvailable()); 1389 // sanity check 1390 assert(dram_pkt->size <= burstSize); 1391 1392 // add a bubble to the data bus, as defined by the 1393 // tRTW when access is to the same rank as previous burst 1394 // Different rank timing is handled with tCS, which is 1395 // applied to colAllowedAt 1396 if (switched_cmd_type && dram_pkt->rank == activeRank) { 1397 busBusyUntil += tRTW; 1398 } 1399 1400 doDRAMAccess(dram_pkt); 1401 1402 writeQueue.pop_front(); 1403 delete dram_pkt; 1404 1405 // If we emptied the write queue, or got sufficiently below the 1406 // threshold (using the minWritesPerSwitch as the hysteresis) and 1407 // are not draining, or we have reads waiting and have done enough 1408 // writes, then switch to reads. 1409 if (writeQueue.empty() || 1410 (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 1411 !drainManager) || 1412 (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 1413 // turn the bus back around for reads again 1414 busState = WRITE_TO_READ; 1415 1416 // note that the we switch back to reads also in the idle 1417 // case, which eventually will check for any draining and 1418 // also pause any further scheduling if there is really 1419 // nothing to do 1420 } 1421 } 1422 // It is possible that a refresh to another rank kicks things back into 1423 // action before reaching this point. 1424 if (!nextReqEvent.scheduled()) 1425 schedule(nextReqEvent, std::max(nextReqTime, curTick())); 1426 1427 // If there is space available and we have writes waiting then let 1428 // them retry. This is done here to ensure that the retry does not 1429 // cause a nextReqEvent to be scheduled before we do so as part of 1430 // the next request processing 1431 if (retryWrReq && writeQueue.size() < writeBufferSize) { 1432 retryWrReq = false; 1433 port.sendRetry(); 1434 } 1435} 1436 1437uint64_t 1438DRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 1439 bool switched_cmd_type) const 1440{ 1441 uint64_t bank_mask = 0; 1442 Tick min_act_at = MaxTick; 1443 1444 uint64_t bank_mask_same_rank = 0; 1445 Tick min_act_at_same_rank = MaxTick; 1446 1447 // Give precedence to commands that access same rank as previous command 1448 bool same_rank_match = false; 1449 1450 // determine if we have queued transactions targetting the 1451 // bank in question 1452 vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 1453 for (const auto& p : queue) { 1454 if(p->rankRef.isAvailable()) 1455 got_waiting[p->bankId] = true; 1456 } 1457 1458 for (int i = 0; i < ranksPerChannel; i++) { 1459 for (int j = 0; j < banksPerRank; j++) { 1460 uint16_t bank_id = i * banksPerRank + j; 1461 1462 // if we have waiting requests for the bank, and it is 1463 // amongst the first available, update the mask 1464 if (got_waiting[bank_id]) { 1465 // make sure this rank is not currently refreshing. 1466 assert(ranks[i]->isAvailable()); 1467 // simplistic approximation of when the bank can issue 1468 // an activate, ignoring any rank-to-rank switching 1469 // cost in this calculation 1470 Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 1471 ranks[i]->banks[j].actAllowedAt : 1472 std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 1473 1474 // prioritize commands that access the 1475 // same rank as previous burst 1476 // Calculate bank mask separately for the case and 1477 // evaluate after loop iterations complete 1478 if (i == activeRank && ranksPerChannel > 1) { 1479 if (act_at <= min_act_at_same_rank) { 1480 // reset same rank bank mask if new minimum is found 1481 // and previous minimum could not immediately send ACT 1482 if (act_at < min_act_at_same_rank && 1483 min_act_at_same_rank > curTick()) 1484 bank_mask_same_rank = 0; 1485 1486 // Set flag indicating that a same rank 1487 // opportunity was found 1488 same_rank_match = true; 1489 1490 // set the bit corresponding to the available bank 1491 replaceBits(bank_mask_same_rank, bank_id, bank_id, 1); 1492 min_act_at_same_rank = act_at; 1493 } 1494 } else { 1495 if (act_at <= min_act_at) { 1496 // reset bank mask if new minimum is found 1497 // and either previous minimum could not immediately send ACT 1498 if (act_at < min_act_at && min_act_at > curTick()) 1499 bank_mask = 0; 1500 // set the bit corresponding to the available bank 1501 replaceBits(bank_mask, bank_id, bank_id, 1); 1502 min_act_at = act_at; 1503 } 1504 } 1505 } 1506 } 1507 } 1508 1509 // Determine the earliest time when the next burst can issue based 1510 // on the current busBusyUntil delay. 1511 // Offset by tRCD to correlate with ACT timing variables 1512 Tick min_cmd_at = busBusyUntil - tCL - tRCD; 1513 1514 // if we have multiple ranks and all 1515 // waiting packets are accessing a rank which was previously active 1516 // then bank_mask_same_rank will be set to a value while bank_mask will 1517 // remain 0. In this case, the function should return the value of 1518 // bank_mask_same_rank. 1519 // else if waiting packets access a rank which was previously active and 1520 // other ranks, prioritize same rank accesses that can issue B2B 1521 // Only optimize for same ranks when the command type 1522 // does not change; do not want to unnecessarily incur tWTR 1523 // 1524 // Resulting FCFS prioritization Order is: 1525 // 1) Commands that access the same rank as previous burst 1526 // and can prep the bank seamlessly. 1527 // 2) Commands (any rank) with earliest bank prep 1528 if ((bank_mask == 0) || (!switched_cmd_type && same_rank_match && 1529 min_act_at_same_rank <= min_cmd_at)) { 1530 bank_mask = bank_mask_same_rank; 1531 } 1532 1533 return bank_mask; 1534} 1535 1536DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p) 1537 : EventManager(&_memory), memory(_memory), 1538 pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), pwrStateTick(0), 1539 refreshState(REF_IDLE), refreshDueAt(0), 1540 power(_p, false), numBanksActive(0), 1541 activateEvent(*this), prechargeEvent(*this), 1542 refreshEvent(*this), powerEvent(*this) 1543{ } 1544 1545void 1546DRAMCtrl::Rank::startup(Tick ref_tick) 1547{ 1548 assert(ref_tick > curTick()); 1549 1550 pwrStateTick = curTick(); 1551 1552 // kick off the refresh, and give ourselves enough time to 1553 // precharge 1554 schedule(refreshEvent, ref_tick); 1555} 1556 1557void
| 261} 262 263Tick 264DRAMCtrl::recvAtomic(PacketPtr pkt) 265{ 266 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 267 268 // do the actual memory access and turn the packet into a response 269 access(pkt); 270 271 Tick latency = 0; 272 if (!pkt->memInhibitAsserted() && pkt->hasData()) { 273 // this value is not supposed to be accurate, just enough to 274 // keep things going, mimic a closed page 275 latency = tRP + tRCD + tCL; 276 } 277 return latency; 278} 279 280bool 281DRAMCtrl::readQueueFull(unsigned int neededEntries) const 282{ 283 DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 284 readBufferSize, readQueue.size() + respQueue.size(), 285 neededEntries); 286 287 return 288 (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 289} 290 291bool 292DRAMCtrl::writeQueueFull(unsigned int neededEntries) const 293{ 294 DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 295 writeBufferSize, writeQueue.size(), neededEntries); 296 return (writeQueue.size() + neededEntries) > writeBufferSize; 297} 298 299DRAMCtrl::DRAMPacket* 300DRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 301 bool isRead) 302{ 303 // decode the address based on the address mapping scheme, with 304 // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 305 // channel, respectively 306 uint8_t rank; 307 uint8_t bank; 308 // use a 64-bit unsigned during the computations as the row is 309 // always the top bits, and check before creating the DRAMPacket 310 uint64_t row; 311 312 // truncate the address to a DRAM burst, which makes it unique to 313 // a specific column, row, bank, rank and channel 314 Addr addr = dramPktAddr / burstSize; 315 316 // we have removed the lowest order address bits that denote the 317 // position within the column 318 if (addrMapping == Enums::RoRaBaChCo) { 319 // the lowest order bits denote the column to ensure that 320 // sequential cache lines occupy the same row 321 addr = addr / columnsPerRowBuffer; 322 323 // take out the channel part of the address 324 addr = addr / channels; 325 326 // after the channel bits, get the bank bits to interleave 327 // over the banks 328 bank = addr % banksPerRank; 329 addr = addr / banksPerRank; 330 331 // after the bank, we get the rank bits which thus interleaves 332 // over the ranks 333 rank = addr % ranksPerChannel; 334 addr = addr / ranksPerChannel; 335 336 // lastly, get the row bits 337 row = addr % rowsPerBank; 338 addr = addr / rowsPerBank; 339 } else if (addrMapping == Enums::RoRaBaCoCh) { 340 // take out the lower-order column bits 341 addr = addr / columnsPerStripe; 342 343 // take out the channel part of the address 344 addr = addr / channels; 345 346 // next, the higher-order column bites 347 addr = addr / (columnsPerRowBuffer / columnsPerStripe); 348 349 // after the column bits, we get the bank bits to interleave 350 // over the banks 351 bank = addr % banksPerRank; 352 addr = addr / banksPerRank; 353 354 // after the bank, we get the rank bits which thus interleaves 355 // over the ranks 356 rank = addr % ranksPerChannel; 357 addr = addr / ranksPerChannel; 358 359 // lastly, get the row bits 360 row = addr % rowsPerBank; 361 addr = addr / rowsPerBank; 362 } else if (addrMapping == Enums::RoCoRaBaCh) { 363 // optimise for closed page mode and utilise maximum 364 // parallelism of the DRAM (at the cost of power) 365 366 // take out the lower-order column bits 367 addr = addr / columnsPerStripe; 368 369 // take out the channel part of the address, not that this has 370 // to match with how accesses are interleaved between the 371 // controllers in the address mapping 372 addr = addr / channels; 373 374 // start with the bank bits, as this provides the maximum 375 // opportunity for parallelism between requests 376 bank = addr % banksPerRank; 377 addr = addr / banksPerRank; 378 379 // next get the rank bits 380 rank = addr % ranksPerChannel; 381 addr = addr / ranksPerChannel; 382 383 // next, the higher-order column bites 384 addr = addr / (columnsPerRowBuffer / columnsPerStripe); 385 386 // lastly, get the row bits 387 row = addr % rowsPerBank; 388 addr = addr / rowsPerBank; 389 } else 390 panic("Unknown address mapping policy chosen!"); 391 392 assert(rank < ranksPerChannel); 393 assert(bank < banksPerRank); 394 assert(row < rowsPerBank); 395 assert(row < Bank::NO_ROW); 396 397 DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 398 dramPktAddr, rank, bank, row); 399 400 // create the corresponding DRAM packet with the entry time and 401 // ready time set to the current tick, the latter will be updated 402 // later 403 uint16_t bank_id = banksPerRank * rank + bank; 404 return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 405 size, ranks[rank]->banks[bank], *ranks[rank]); 406} 407 408void 409DRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 410{ 411 // only add to the read queue here. whenever the request is 412 // eventually done, set the readyTime, and call schedule() 413 assert(!pkt->isWrite()); 414 415 assert(pktCount != 0); 416 417 // if the request size is larger than burst size, the pkt is split into 418 // multiple DRAM packets 419 // Note if the pkt starting address is not aligened to burst size, the 420 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 421 // are aligned to burst size boundaries. This is to ensure we accurately 422 // check read packets against packets in write queue. 423 Addr addr = pkt->getAddr(); 424 unsigned pktsServicedByWrQ = 0; 425 BurstHelper* burst_helper = NULL; 426 for (int cnt = 0; cnt < pktCount; ++cnt) { 427 unsigned size = std::min((addr | (burstSize - 1)) + 1, 428 pkt->getAddr() + pkt->getSize()) - addr; 429 readPktSize[ceilLog2(size)]++; 430 readBursts++; 431 432 // First check write buffer to see if the data is already at 433 // the controller 434 bool foundInWrQ = false; 435 for (auto i = writeQueue.begin(); i != writeQueue.end(); ++i) { 436 // check if the read is subsumed in the write entry we are 437 // looking at 438 if ((*i)->addr <= addr && 439 (addr + size) <= ((*i)->addr + (*i)->size)) { 440 foundInWrQ = true; 441 servicedByWrQ++; 442 pktsServicedByWrQ++; 443 DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 444 "write queue\n", addr, size); 445 bytesReadWrQ += burstSize; 446 break; 447 } 448 } 449 450 // If not found in the write q, make a DRAM packet and 451 // push it onto the read queue 452 if (!foundInWrQ) { 453 454 // Make the burst helper for split packets 455 if (pktCount > 1 && burst_helper == NULL) { 456 DPRINTF(DRAM, "Read to addr %lld translates to %d " 457 "dram requests\n", pkt->getAddr(), pktCount); 458 burst_helper = new BurstHelper(pktCount); 459 } 460 461 DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 462 dram_pkt->burstHelper = burst_helper; 463 464 assert(!readQueueFull(1)); 465 rdQLenPdf[readQueue.size() + respQueue.size()]++; 466 467 DPRINTF(DRAM, "Adding to read queue\n"); 468 469 readQueue.push_back(dram_pkt); 470 471 // Update stats 472 avgRdQLen = readQueue.size() + respQueue.size(); 473 } 474 475 // Starting address of next dram pkt (aligend to burstSize boundary) 476 addr = (addr | (burstSize - 1)) + 1; 477 } 478 479 // If all packets are serviced by write queue, we send the repsonse back 480 if (pktsServicedByWrQ == pktCount) { 481 accessAndRespond(pkt, frontendLatency); 482 return; 483 } 484 485 // Update how many split packets are serviced by write queue 486 if (burst_helper != NULL) 487 burst_helper->burstsServiced = pktsServicedByWrQ; 488 489 // If we are not already scheduled to get a request out of the 490 // queue, do so now 491 if (!nextReqEvent.scheduled()) { 492 DPRINTF(DRAM, "Request scheduled immediately\n"); 493 schedule(nextReqEvent, curTick()); 494 } 495} 496 497void 498DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 499{ 500 // only add to the write queue here. whenever the request is 501 // eventually done, set the readyTime, and call schedule() 502 assert(pkt->isWrite()); 503 504 // if the request size is larger than burst size, the pkt is split into 505 // multiple DRAM packets 506 Addr addr = pkt->getAddr(); 507 for (int cnt = 0; cnt < pktCount; ++cnt) { 508 unsigned size = std::min((addr | (burstSize - 1)) + 1, 509 pkt->getAddr() + pkt->getSize()) - addr; 510 writePktSize[ceilLog2(size)]++; 511 writeBursts++; 512 513 // see if we can merge with an existing item in the write 514 // queue and keep track of whether we have merged or not so we 515 // can stop at that point and also avoid enqueueing a new 516 // request 517 bool merged = false; 518 auto w = writeQueue.begin(); 519 520 while(!merged && w != writeQueue.end()) { 521 // either of the two could be first, if they are the same 522 // it does not matter which way we go 523 if ((*w)->addr >= addr) { 524 // the existing one starts after the new one, figure 525 // out where the new one ends with respect to the 526 // existing one 527 if ((addr + size) >= ((*w)->addr + (*w)->size)) { 528 // check if the existing one is completely 529 // subsumed in the new one 530 DPRINTF(DRAM, "Merging write covering existing burst\n"); 531 merged = true; 532 // update both the address and the size 533 (*w)->addr = addr; 534 (*w)->size = size; 535 } else if ((addr + size) >= (*w)->addr && 536 ((*w)->addr + (*w)->size - addr) <= burstSize) { 537 // the new one is just before or partially 538 // overlapping with the existing one, and together 539 // they fit within a burst 540 DPRINTF(DRAM, "Merging write before existing burst\n"); 541 merged = true; 542 // the existing queue item needs to be adjusted with 543 // respect to both address and size 544 (*w)->size = (*w)->addr + (*w)->size - addr; 545 (*w)->addr = addr; 546 } 547 } else { 548 // the new one starts after the current one, figure 549 // out where the existing one ends with respect to the 550 // new one 551 if (((*w)->addr + (*w)->size) >= (addr + size)) { 552 // check if the new one is completely subsumed in the 553 // existing one 554 DPRINTF(DRAM, "Merging write into existing burst\n"); 555 merged = true; 556 // no adjustments necessary 557 } else if (((*w)->addr + (*w)->size) >= addr && 558 (addr + size - (*w)->addr) <= burstSize) { 559 // the existing one is just before or partially 560 // overlapping with the new one, and together 561 // they fit within a burst 562 DPRINTF(DRAM, "Merging write after existing burst\n"); 563 merged = true; 564 // the address is right, and only the size has 565 // to be adjusted 566 (*w)->size = addr + size - (*w)->addr; 567 } 568 } 569 ++w; 570 } 571 572 // if the item was not merged we need to create a new write 573 // and enqueue it 574 if (!merged) { 575 DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 576 577 assert(writeQueue.size() < writeBufferSize); 578 wrQLenPdf[writeQueue.size()]++; 579 580 DPRINTF(DRAM, "Adding to write queue\n"); 581 582 writeQueue.push_back(dram_pkt); 583 584 // Update stats 585 avgWrQLen = writeQueue.size(); 586 } else { 587 // keep track of the fact that this burst effectively 588 // disappeared as it was merged with an existing one 589 mergedWrBursts++; 590 } 591 592 // Starting address of next dram pkt (aligend to burstSize boundary) 593 addr = (addr | (burstSize - 1)) + 1; 594 } 595 596 // we do not wait for the writes to be send to the actual memory, 597 // but instead take responsibility for the consistency here and 598 // snoop the write queue for any upcoming reads 599 // @todo, if a pkt size is larger than burst size, we might need a 600 // different front end latency 601 accessAndRespond(pkt, frontendLatency); 602 603 // If we are not already scheduled to get a request out of the 604 // queue, do so now 605 if (!nextReqEvent.scheduled()) { 606 DPRINTF(DRAM, "Request scheduled immediately\n"); 607 schedule(nextReqEvent, curTick()); 608 } 609} 610 611void 612DRAMCtrl::printQs() const { 613 DPRINTF(DRAM, "===READ QUEUE===\n\n"); 614 for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 615 DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 616 } 617 DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 618 for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 619 DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 620 } 621 DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 622 for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 623 DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 624 } 625} 626 627bool 628DRAMCtrl::recvTimingReq(PacketPtr pkt) 629{ 630 /// @todo temporary hack to deal with memory corruption issues until 631 /// 4-phase transactions are complete 632 for (int x = 0; x < pendingDelete.size(); x++) 633 delete pendingDelete[x]; 634 pendingDelete.clear(); 635 636 // This is where we enter from the outside world 637 DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 638 pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 639 640 // simply drop inhibited packets for now 641 if (pkt->memInhibitAsserted()) { 642 DPRINTF(DRAM, "Inhibited packet -- Dropping it now\n"); 643 pendingDelete.push_back(pkt); 644 return true; 645 } 646 647 // Calc avg gap between requests 648 if (prevArrival != 0) { 649 totGap += curTick() - prevArrival; 650 } 651 prevArrival = curTick(); 652 653 654 // Find out how many dram packets a pkt translates to 655 // If the burst size is equal or larger than the pkt size, then a pkt 656 // translates to only one dram packet. Otherwise, a pkt translates to 657 // multiple dram packets 658 unsigned size = pkt->getSize(); 659 unsigned offset = pkt->getAddr() & (burstSize - 1); 660 unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 661 662 // check local buffers and do not accept if full 663 if (pkt->isRead()) { 664 assert(size != 0); 665 if (readQueueFull(dram_pkt_count)) { 666 DPRINTF(DRAM, "Read queue full, not accepting\n"); 667 // remember that we have to retry this port 668 retryRdReq = true; 669 numRdRetry++; 670 return false; 671 } else { 672 addToReadQueue(pkt, dram_pkt_count); 673 readReqs++; 674 bytesReadSys += size; 675 } 676 } else if (pkt->isWrite()) { 677 assert(size != 0); 678 if (writeQueueFull(dram_pkt_count)) { 679 DPRINTF(DRAM, "Write queue full, not accepting\n"); 680 // remember that we have to retry this port 681 retryWrReq = true; 682 numWrRetry++; 683 return false; 684 } else { 685 addToWriteQueue(pkt, dram_pkt_count); 686 writeReqs++; 687 bytesWrittenSys += size; 688 } 689 } else { 690 DPRINTF(DRAM,"Neither read nor write, ignore timing\n"); 691 neitherReadNorWrite++; 692 accessAndRespond(pkt, 1); 693 } 694 695 return true; 696} 697 698void 699DRAMCtrl::processRespondEvent() 700{ 701 DPRINTF(DRAM, 702 "processRespondEvent(): Some req has reached its readyTime\n"); 703 704 DRAMPacket* dram_pkt = respQueue.front(); 705 706 if (dram_pkt->burstHelper) { 707 // it is a split packet 708 dram_pkt->burstHelper->burstsServiced++; 709 if (dram_pkt->burstHelper->burstsServiced == 710 dram_pkt->burstHelper->burstCount) { 711 // we have now serviced all children packets of a system packet 712 // so we can now respond to the requester 713 // @todo we probably want to have a different front end and back 714 // end latency for split packets 715 accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 716 delete dram_pkt->burstHelper; 717 dram_pkt->burstHelper = NULL; 718 } 719 } else { 720 // it is not a split packet 721 accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 722 } 723 724 delete respQueue.front(); 725 respQueue.pop_front(); 726 727 if (!respQueue.empty()) { 728 assert(respQueue.front()->readyTime >= curTick()); 729 assert(!respondEvent.scheduled()); 730 schedule(respondEvent, respQueue.front()->readyTime); 731 } else { 732 // if there is nothing left in any queue, signal a drain 733 if (writeQueue.empty() && readQueue.empty() && 734 drainManager) { 735 DPRINTF(Drain, "DRAM controller done draining\n"); 736 drainManager->signalDrainDone(); 737 drainManager = NULL; 738 } 739 } 740 741 // We have made a location in the queue available at this point, 742 // so if there is a read that was forced to wait, retry now 743 if (retryRdReq) { 744 retryRdReq = false; 745 port.sendRetry(); 746 } 747} 748 749bool 750DRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 751{ 752 // This method does the arbitration between requests. The chosen 753 // packet is simply moved to the head of the queue. The other 754 // methods know that this is the place to look. For example, with 755 // FCFS, this method does nothing 756 assert(!queue.empty()); 757 758 // bool to indicate if a packet to an available rank is found 759 bool found_packet = false; 760 if (queue.size() == 1) { 761 DRAMPacket* dram_pkt = queue.front(); 762 // available rank corresponds to state refresh idle 763 if (ranks[dram_pkt->rank]->isAvailable()) { 764 found_packet = true; 765 DPRINTF(DRAM, "Single request, going to a free rank\n"); 766 } else { 767 DPRINTF(DRAM, "Single request, going to a busy rank\n"); 768 } 769 return found_packet; 770 } 771 772 if (memSchedPolicy == Enums::fcfs) { 773 // check if there is a packet going to a free rank 774 for(auto i = queue.begin(); i != queue.end() ; ++i) { 775 DRAMPacket* dram_pkt = *i; 776 if (ranks[dram_pkt->rank]->isAvailable()) { 777 queue.erase(i); 778 queue.push_front(dram_pkt); 779 found_packet = true; 780 break; 781 } 782 } 783 } else if (memSchedPolicy == Enums::frfcfs) { 784 found_packet = reorderQueue(queue, switched_cmd_type); 785 } else 786 panic("No scheduling policy chosen\n"); 787 return found_packet; 788} 789 790bool 791DRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type) 792{ 793 // Only determine this when needed 794 uint64_t earliest_banks = 0; 795 796 // Search for row hits first, if no row hit is found then schedule the 797 // packet to one of the earliest banks available 798 bool found_packet = false; 799 bool found_earliest_pkt = false; 800 bool found_prepped_diff_rank_pkt = false; 801 auto selected_pkt_it = queue.end(); 802 803 for (auto i = queue.begin(); i != queue.end() ; ++i) { 804 DRAMPacket* dram_pkt = *i; 805 const Bank& bank = dram_pkt->bankRef; 806 // check if rank is busy. If this is the case jump to the next packet 807 // Check if it is a row hit 808 if (dram_pkt->rankRef.isAvailable()) { 809 if (bank.openRow == dram_pkt->row) { 810 if (dram_pkt->rank == activeRank || switched_cmd_type) { 811 // FCFS within the hits, giving priority to commands 812 // that access the same rank as the previous burst 813 // to minimize bus turnaround delays 814 // Only give rank prioity when command type is 815 // not changing 816 DPRINTF(DRAM, "Row buffer hit\n"); 817 selected_pkt_it = i; 818 break; 819 } else if (!found_prepped_diff_rank_pkt) { 820 // found row hit for command on different rank 821 // than prev burst 822 selected_pkt_it = i; 823 found_prepped_diff_rank_pkt = true; 824 } 825 } else if (!found_earliest_pkt & !found_prepped_diff_rank_pkt) { 826 // packet going to a rank which is currently not waiting for a 827 // refresh, No row hit and 828 // haven't found an entry with a row hit to a new rank 829 if (earliest_banks == 0) 830 // Determine entries with earliest bank prep delay 831 // Function will give priority to commands that access the 832 // same rank as previous burst and can prep 833 // the bank seamlessly 834 earliest_banks = minBankPrep(queue, switched_cmd_type); 835 836 // FCFS - Bank is first available bank 837 if (bits(earliest_banks, dram_pkt->bankId, 838 dram_pkt->bankId)) { 839 // Remember the packet to be scheduled to one of 840 // the earliest banks available, FCFS amongst the 841 // earliest banks 842 selected_pkt_it = i; 843 //if the packet found is going to a rank that is currently 844 //not busy then update the found_packet to true 845 found_earliest_pkt = true; 846 } 847 } 848 } 849 } 850 851 if (selected_pkt_it != queue.end()) { 852 DRAMPacket* selected_pkt = *selected_pkt_it; 853 queue.erase(selected_pkt_it); 854 queue.push_front(selected_pkt); 855 found_packet = true; 856 } 857 return found_packet; 858} 859 860void 861DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 862{ 863 DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 864 865 bool needsResponse = pkt->needsResponse(); 866 // do the actual memory access which also turns the packet into a 867 // response 868 access(pkt); 869 870 // turn packet around to go back to requester if response expected 871 if (needsResponse) { 872 // access already turned the packet into a response 873 assert(pkt->isResponse()); 874 875 // @todo someone should pay for this 876 pkt->firstWordDelay = pkt->lastWordDelay = 0; 877 878 // queue the packet in the response queue to be sent out after 879 // the static latency has passed 880 port.schedTimingResp(pkt, curTick() + static_latency); 881 } else { 882 // @todo the packet is going to be deleted, and the DRAMPacket 883 // is still having a pointer to it 884 pendingDelete.push_back(pkt); 885 } 886 887 DPRINTF(DRAM, "Done\n"); 888 889 return; 890} 891 892void 893DRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 894 Tick act_tick, uint32_t row) 895{ 896 assert(rank_ref.actTicks.size() == activationLimit); 897 898 DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 899 900 // update the open row 901 assert(bank_ref.openRow == Bank::NO_ROW); 902 bank_ref.openRow = row; 903 904 // start counting anew, this covers both the case when we 905 // auto-precharged, and when this access is forced to 906 // precharge 907 bank_ref.bytesAccessed = 0; 908 bank_ref.rowAccesses = 0; 909 910 ++rank_ref.numBanksActive; 911 assert(rank_ref.numBanksActive <= banksPerRank); 912 913 DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 914 bank_ref.bank, rank_ref.rank, act_tick, 915 ranks[rank_ref.rank]->numBanksActive); 916 917 rank_ref.power.powerlib.doCommand(MemCommand::ACT, bank_ref.bank, 918 divCeil(act_tick, tCK) - 919 timeStampOffset); 920 921 DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 922 timeStampOffset, bank_ref.bank, rank_ref.rank); 923 924 // The next access has to respect tRAS for this bank 925 bank_ref.preAllowedAt = act_tick + tRAS; 926 927 // Respect the row-to-column command delay 928 bank_ref.colAllowedAt = std::max(act_tick + tRCD, bank_ref.colAllowedAt); 929 930 // start by enforcing tRRD 931 for(int i = 0; i < banksPerRank; i++) { 932 // next activate to any bank in this rank must not happen 933 // before tRRD 934 if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 935 // bank group architecture requires longer delays between 936 // ACT commands within the same bank group. Use tRRD_L 937 // in this case 938 rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 939 rank_ref.banks[i].actAllowedAt); 940 } else { 941 // use shorter tRRD value when either 942 // 1) bank group architecture is not supportted 943 // 2) bank is in a different bank group 944 rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 945 rank_ref.banks[i].actAllowedAt); 946 } 947 } 948 949 // next, we deal with tXAW, if the activation limit is disabled 950 // then we directly schedule an activate power event 951 if (!rank_ref.actTicks.empty()) { 952 // sanity check 953 if (rank_ref.actTicks.back() && 954 (act_tick - rank_ref.actTicks.back()) < tXAW) { 955 panic("Got %d activates in window %d (%llu - %llu) which " 956 "is smaller than %llu\n", activationLimit, act_tick - 957 rank_ref.actTicks.back(), act_tick, 958 rank_ref.actTicks.back(), tXAW); 959 } 960 961 // shift the times used for the book keeping, the last element 962 // (highest index) is the oldest one and hence the lowest value 963 rank_ref.actTicks.pop_back(); 964 965 // record an new activation (in the future) 966 rank_ref.actTicks.push_front(act_tick); 967 968 // cannot activate more than X times in time window tXAW, push the 969 // next one (the X + 1'st activate) to be tXAW away from the 970 // oldest in our window of X 971 if (rank_ref.actTicks.back() && 972 (act_tick - rank_ref.actTicks.back()) < tXAW) { 973 DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 974 "no earlier than %llu\n", activationLimit, 975 rank_ref.actTicks.back() + tXAW); 976 for(int j = 0; j < banksPerRank; j++) 977 // next activate must not happen before end of window 978 rank_ref.banks[j].actAllowedAt = 979 std::max(rank_ref.actTicks.back() + tXAW, 980 rank_ref.banks[j].actAllowedAt); 981 } 982 } 983 984 // at the point when this activate takes place, make sure we 985 // transition to the active power state 986 if (!rank_ref.activateEvent.scheduled()) 987 schedule(rank_ref.activateEvent, act_tick); 988 else if (rank_ref.activateEvent.when() > act_tick) 989 // move it sooner in time 990 reschedule(rank_ref.activateEvent, act_tick); 991} 992 993void 994DRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 995{ 996 // make sure the bank has an open row 997 assert(bank.openRow != Bank::NO_ROW); 998 999 // sample the bytes per activate here since we are closing 1000 // the page 1001 bytesPerActivate.sample(bank.bytesAccessed); 1002 1003 bank.openRow = Bank::NO_ROW; 1004 1005 // no precharge allowed before this one 1006 bank.preAllowedAt = pre_at; 1007 1008 Tick pre_done_at = pre_at + tRP; 1009 1010 bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 1011 1012 assert(rank_ref.numBanksActive != 0); 1013 --rank_ref.numBanksActive; 1014 1015 DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 1016 "%d active\n", bank.bank, rank_ref.rank, pre_at, 1017 rank_ref.numBanksActive); 1018 1019 if (trace) { 1020 1021 rank_ref.power.powerlib.doCommand(MemCommand::PRE, bank.bank, 1022 divCeil(pre_at, tCK) - 1023 timeStampOffset); 1024 DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 1025 timeStampOffset, bank.bank, rank_ref.rank); 1026 } 1027 // if we look at the current number of active banks we might be 1028 // tempted to think the DRAM is now idle, however this can be 1029 // undone by an activate that is scheduled to happen before we 1030 // would have reached the idle state, so schedule an event and 1031 // rather check once we actually make it to the point in time when 1032 // the (last) precharge takes place 1033 if (!rank_ref.prechargeEvent.scheduled()) 1034 schedule(rank_ref.prechargeEvent, pre_done_at); 1035 else if (rank_ref.prechargeEvent.when() < pre_done_at) 1036 reschedule(rank_ref.prechargeEvent, pre_done_at); 1037} 1038 1039void 1040DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 1041{ 1042 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 1043 dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 1044 1045 // get the rank 1046 Rank& rank = dram_pkt->rankRef; 1047 1048 // get the bank 1049 Bank& bank = dram_pkt->bankRef; 1050 1051 // for the state we need to track if it is a row hit or not 1052 bool row_hit = true; 1053 1054 // respect any constraints on the command (e.g. tRCD or tCCD) 1055 Tick cmd_at = std::max(bank.colAllowedAt, curTick()); 1056 1057 // Determine the access latency and update the bank state 1058 if (bank.openRow == dram_pkt->row) { 1059 // nothing to do 1060 } else { 1061 row_hit = false; 1062 1063 // If there is a page open, precharge it. 1064 if (bank.openRow != Bank::NO_ROW) { 1065 prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 1066 } 1067 1068 // next we need to account for the delay in activating the 1069 // page 1070 Tick act_tick = std::max(bank.actAllowedAt, curTick()); 1071 1072 // Record the activation and deal with all the global timing 1073 // constraints caused be a new activation (tRRD and tXAW) 1074 activateBank(rank, bank, act_tick, dram_pkt->row); 1075 1076 // issue the command as early as possible 1077 cmd_at = bank.colAllowedAt; 1078 } 1079 1080 // we need to wait until the bus is available before we can issue 1081 // the command 1082 cmd_at = std::max(cmd_at, busBusyUntil - tCL); 1083 1084 // update the packet ready time 1085 dram_pkt->readyTime = cmd_at + tCL + tBURST; 1086 1087 // only one burst can use the bus at any one point in time 1088 assert(dram_pkt->readyTime - busBusyUntil >= tBURST); 1089 1090 // update the time for the next read/write burst for each 1091 // bank (add a max with tCCD/tCCD_L here) 1092 Tick cmd_dly; 1093 for(int j = 0; j < ranksPerChannel; j++) { 1094 for(int i = 0; i < banksPerRank; i++) { 1095 // next burst to same bank group in this rank must not happen 1096 // before tCCD_L. Different bank group timing requirement is 1097 // tBURST; Add tCS for different ranks 1098 if (dram_pkt->rank == j) { 1099 if (bankGroupArch && 1100 (bank.bankgr == ranks[j]->banks[i].bankgr)) { 1101 // bank group architecture requires longer delays between 1102 // RD/WR burst commands to the same bank group. 1103 // Use tCCD_L in this case 1104 cmd_dly = tCCD_L; 1105 } else { 1106 // use tBURST (equivalent to tCCD_S), the shorter 1107 // cas-to-cas delay value, when either: 1108 // 1) bank group architecture is not supportted 1109 // 2) bank is in a different bank group 1110 cmd_dly = tBURST; 1111 } 1112 } else { 1113 // different rank is by default in a different bank group 1114 // use tBURST (equivalent to tCCD_S), which is the shorter 1115 // cas-to-cas delay in this case 1116 // Add tCS to account for rank-to-rank bus delay requirements 1117 cmd_dly = tBURST + tCS; 1118 } 1119 ranks[j]->banks[i].colAllowedAt = std::max(cmd_at + cmd_dly, 1120 ranks[j]->banks[i].colAllowedAt); 1121 } 1122 } 1123 1124 // Save rank of current access 1125 activeRank = dram_pkt->rank; 1126 1127 // If this is a write, we also need to respect the write recovery 1128 // time before a precharge, in the case of a read, respect the 1129 // read to precharge constraint 1130 bank.preAllowedAt = std::max(bank.preAllowedAt, 1131 dram_pkt->isRead ? cmd_at + tRTP : 1132 dram_pkt->readyTime + tWR); 1133 1134 // increment the bytes accessed and the accesses per row 1135 bank.bytesAccessed += burstSize; 1136 ++bank.rowAccesses; 1137 1138 // if we reached the max, then issue with an auto-precharge 1139 bool auto_precharge = pageMgmt == Enums::close || 1140 bank.rowAccesses == maxAccessesPerRow; 1141 1142 // if we did not hit the limit, we might still want to 1143 // auto-precharge 1144 if (!auto_precharge && 1145 (pageMgmt == Enums::open_adaptive || 1146 pageMgmt == Enums::close_adaptive)) { 1147 // a twist on the open and close page policies: 1148 // 1) open_adaptive page policy does not blindly keep the 1149 // page open, but close it if there are no row hits, and there 1150 // are bank conflicts in the queue 1151 // 2) close_adaptive page policy does not blindly close the 1152 // page, but closes it only if there are no row hits in the queue. 1153 // In this case, only force an auto precharge when there 1154 // are no same page hits in the queue 1155 bool got_more_hits = false; 1156 bool got_bank_conflict = false; 1157 1158 // either look at the read queue or write queue 1159 const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 1160 writeQueue; 1161 auto p = queue.begin(); 1162 // make sure we are not considering the packet that we are 1163 // currently dealing with (which is the head of the queue) 1164 ++p; 1165 1166 // keep on looking until we have found required condition or 1167 // reached the end 1168 while (!(got_more_hits && 1169 (got_bank_conflict || pageMgmt == Enums::close_adaptive)) && 1170 p != queue.end()) { 1171 bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 1172 (dram_pkt->bank == (*p)->bank); 1173 bool same_row = dram_pkt->row == (*p)->row; 1174 got_more_hits |= same_rank_bank && same_row; 1175 got_bank_conflict |= same_rank_bank && !same_row; 1176 ++p; 1177 } 1178 1179 // auto pre-charge when either 1180 // 1) open_adaptive policy, we have not got any more hits, and 1181 // have a bank conflict 1182 // 2) close_adaptive policy and we have not got any more hits 1183 auto_precharge = !got_more_hits && 1184 (got_bank_conflict || pageMgmt == Enums::close_adaptive); 1185 } 1186 1187 // DRAMPower trace command to be written 1188 std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 1189 1190 // MemCommand required for DRAMPower library 1191 MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 1192 MemCommand::WR; 1193 1194 // if this access should use auto-precharge, then we are 1195 // closing the row 1196 if (auto_precharge) { 1197 // if auto-precharge push a PRE command at the correct tick to the 1198 // list used by DRAMPower library to calculate power 1199 prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 1200 1201 DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 1202 } 1203 1204 // Update bus state 1205 busBusyUntil = dram_pkt->readyTime; 1206 1207 DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n", 1208 dram_pkt->addr, dram_pkt->readyTime, busBusyUntil); 1209 1210 dram_pkt->rankRef.power.powerlib.doCommand(command, dram_pkt->bank, 1211 divCeil(cmd_at, tCK) - 1212 timeStampOffset); 1213 1214 DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 1215 timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 1216 1217 // Update the minimum timing between the requests, this is a 1218 // conservative estimate of when we have to schedule the next 1219 // request to not introduce any unecessary bubbles. In most cases 1220 // we will wake up sooner than we have to. 1221 nextReqTime = busBusyUntil - (tRP + tRCD + tCL); 1222 1223 // Update the stats and schedule the next request 1224 if (dram_pkt->isRead) { 1225 ++readsThisTime; 1226 if (row_hit) 1227 readRowHits++; 1228 bytesReadDRAM += burstSize; 1229 perBankRdBursts[dram_pkt->bankId]++; 1230 1231 // Update latency stats 1232 totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 1233 totBusLat += tBURST; 1234 totQLat += cmd_at - dram_pkt->entryTime; 1235 } else { 1236 ++writesThisTime; 1237 if (row_hit) 1238 writeRowHits++; 1239 bytesWritten += burstSize; 1240 perBankWrBursts[dram_pkt->bankId]++; 1241 } 1242} 1243 1244void 1245DRAMCtrl::processNextReqEvent() 1246{ 1247 int busyRanks = 0; 1248 for (auto r : ranks) { 1249 if (!r->isAvailable()) { 1250 // rank is busy refreshing 1251 busyRanks++; 1252 1253 // let the rank know that if it was waiting to drain, it 1254 // is now done and ready to proceed 1255 r->checkDrainDone(); 1256 } 1257 } 1258 1259 if (busyRanks == ranksPerChannel) { 1260 // if all ranks are refreshing wait for them to finish 1261 // and stall this state machine without taking any further 1262 // action, and do not schedule a new nextReqEvent 1263 return; 1264 } 1265 1266 // pre-emptively set to false. Overwrite if in READ_TO_WRITE 1267 // or WRITE_TO_READ state 1268 bool switched_cmd_type = false; 1269 if (busState == READ_TO_WRITE) { 1270 DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 1271 "waiting\n", readsThisTime, readQueue.size()); 1272 1273 // sample and reset the read-related stats as we are now 1274 // transitioning to writes, and all reads are done 1275 rdPerTurnAround.sample(readsThisTime); 1276 readsThisTime = 0; 1277 1278 // now proceed to do the actual writes 1279 busState = WRITE; 1280 switched_cmd_type = true; 1281 } else if (busState == WRITE_TO_READ) { 1282 DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 1283 "waiting\n", writesThisTime, writeQueue.size()); 1284 1285 wrPerTurnAround.sample(writesThisTime); 1286 writesThisTime = 0; 1287 1288 busState = READ; 1289 switched_cmd_type = true; 1290 } 1291 1292 // when we get here it is either a read or a write 1293 if (busState == READ) { 1294 1295 // track if we should switch or not 1296 bool switch_to_writes = false; 1297 1298 if (readQueue.empty()) { 1299 // In the case there is no read request to go next, 1300 // trigger writes if we have passed the low threshold (or 1301 // if we are draining) 1302 if (!writeQueue.empty() && 1303 (drainManager || writeQueue.size() > writeLowThreshold)) { 1304 1305 switch_to_writes = true; 1306 } else { 1307 // check if we are drained 1308 if (respQueue.empty () && drainManager) { 1309 DPRINTF(Drain, "DRAM controller done draining\n"); 1310 drainManager->signalDrainDone(); 1311 drainManager = NULL; 1312 } 1313 1314 // nothing to do, not even any point in scheduling an 1315 // event for the next request 1316 return; 1317 } 1318 } else { 1319 // bool to check if there is a read to a free rank 1320 bool found_read = false; 1321 1322 // Figure out which read request goes next, and move it to the 1323 // front of the read queue 1324 found_read = chooseNext(readQueue, switched_cmd_type); 1325 1326 // if no read to an available rank is found then return 1327 // at this point. There could be writes to the available ranks 1328 // which are above the required threshold. However, to 1329 // avoid adding more complexity to the code, return and wait 1330 // for a refresh event to kick things into action again. 1331 if (!found_read) 1332 return; 1333 1334 DRAMPacket* dram_pkt = readQueue.front(); 1335 assert(dram_pkt->rankRef.isAvailable()); 1336 // here we get a bit creative and shift the bus busy time not 1337 // just the tWTR, but also a CAS latency to capture the fact 1338 // that we are allowed to prepare a new bank, but not issue a 1339 // read command until after tWTR, in essence we capture a 1340 // bubble on the data bus that is tWTR + tCL 1341 if (switched_cmd_type && dram_pkt->rank == activeRank) { 1342 busBusyUntil += tWTR + tCL; 1343 } 1344 1345 doDRAMAccess(dram_pkt); 1346 1347 // At this point we're done dealing with the request 1348 readQueue.pop_front(); 1349 1350 // sanity check 1351 assert(dram_pkt->size <= burstSize); 1352 assert(dram_pkt->readyTime >= curTick()); 1353 1354 // Insert into response queue. It will be sent back to the 1355 // requestor at its readyTime 1356 if (respQueue.empty()) { 1357 assert(!respondEvent.scheduled()); 1358 schedule(respondEvent, dram_pkt->readyTime); 1359 } else { 1360 assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 1361 assert(respondEvent.scheduled()); 1362 } 1363 1364 respQueue.push_back(dram_pkt); 1365 1366 // we have so many writes that we have to transition 1367 if (writeQueue.size() > writeHighThreshold) { 1368 switch_to_writes = true; 1369 } 1370 } 1371 1372 // switching to writes, either because the read queue is empty 1373 // and the writes have passed the low threshold (or we are 1374 // draining), or because the writes hit the hight threshold 1375 if (switch_to_writes) { 1376 // transition to writing 1377 busState = READ_TO_WRITE; 1378 } 1379 } else { 1380 // bool to check if write to free rank is found 1381 bool found_write = false; 1382 1383 found_write = chooseNext(writeQueue, switched_cmd_type); 1384 1385 // if no writes to an available rank are found then return. 1386 // There could be reads to the available ranks. However, to avoid 1387 // adding more complexity to the code, return at this point and wait 1388 // for a refresh event to kick things into action again. 1389 if (!found_write) 1390 return; 1391 1392 DRAMPacket* dram_pkt = writeQueue.front(); 1393 assert(dram_pkt->rankRef.isAvailable()); 1394 // sanity check 1395 assert(dram_pkt->size <= burstSize); 1396 1397 // add a bubble to the data bus, as defined by the 1398 // tRTW when access is to the same rank as previous burst 1399 // Different rank timing is handled with tCS, which is 1400 // applied to colAllowedAt 1401 if (switched_cmd_type && dram_pkt->rank == activeRank) { 1402 busBusyUntil += tRTW; 1403 } 1404 1405 doDRAMAccess(dram_pkt); 1406 1407 writeQueue.pop_front(); 1408 delete dram_pkt; 1409 1410 // If we emptied the write queue, or got sufficiently below the 1411 // threshold (using the minWritesPerSwitch as the hysteresis) and 1412 // are not draining, or we have reads waiting and have done enough 1413 // writes, then switch to reads. 1414 if (writeQueue.empty() || 1415 (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 1416 !drainManager) || 1417 (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 1418 // turn the bus back around for reads again 1419 busState = WRITE_TO_READ; 1420 1421 // note that the we switch back to reads also in the idle 1422 // case, which eventually will check for any draining and 1423 // also pause any further scheduling if there is really 1424 // nothing to do 1425 } 1426 } 1427 // It is possible that a refresh to another rank kicks things back into 1428 // action before reaching this point. 1429 if (!nextReqEvent.scheduled()) 1430 schedule(nextReqEvent, std::max(nextReqTime, curTick())); 1431 1432 // If there is space available and we have writes waiting then let 1433 // them retry. This is done here to ensure that the retry does not 1434 // cause a nextReqEvent to be scheduled before we do so as part of 1435 // the next request processing 1436 if (retryWrReq && writeQueue.size() < writeBufferSize) { 1437 retryWrReq = false; 1438 port.sendRetry(); 1439 } 1440} 1441 1442uint64_t 1443DRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 1444 bool switched_cmd_type) const 1445{ 1446 uint64_t bank_mask = 0; 1447 Tick min_act_at = MaxTick; 1448 1449 uint64_t bank_mask_same_rank = 0; 1450 Tick min_act_at_same_rank = MaxTick; 1451 1452 // Give precedence to commands that access same rank as previous command 1453 bool same_rank_match = false; 1454 1455 // determine if we have queued transactions targetting the 1456 // bank in question 1457 vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 1458 for (const auto& p : queue) { 1459 if(p->rankRef.isAvailable()) 1460 got_waiting[p->bankId] = true; 1461 } 1462 1463 for (int i = 0; i < ranksPerChannel; i++) { 1464 for (int j = 0; j < banksPerRank; j++) { 1465 uint16_t bank_id = i * banksPerRank + j; 1466 1467 // if we have waiting requests for the bank, and it is 1468 // amongst the first available, update the mask 1469 if (got_waiting[bank_id]) { 1470 // make sure this rank is not currently refreshing. 1471 assert(ranks[i]->isAvailable()); 1472 // simplistic approximation of when the bank can issue 1473 // an activate, ignoring any rank-to-rank switching 1474 // cost in this calculation 1475 Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 1476 ranks[i]->banks[j].actAllowedAt : 1477 std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 1478 1479 // prioritize commands that access the 1480 // same rank as previous burst 1481 // Calculate bank mask separately for the case and 1482 // evaluate after loop iterations complete 1483 if (i == activeRank && ranksPerChannel > 1) { 1484 if (act_at <= min_act_at_same_rank) { 1485 // reset same rank bank mask if new minimum is found 1486 // and previous minimum could not immediately send ACT 1487 if (act_at < min_act_at_same_rank && 1488 min_act_at_same_rank > curTick()) 1489 bank_mask_same_rank = 0; 1490 1491 // Set flag indicating that a same rank 1492 // opportunity was found 1493 same_rank_match = true; 1494 1495 // set the bit corresponding to the available bank 1496 replaceBits(bank_mask_same_rank, bank_id, bank_id, 1); 1497 min_act_at_same_rank = act_at; 1498 } 1499 } else { 1500 if (act_at <= min_act_at) { 1501 // reset bank mask if new minimum is found 1502 // and either previous minimum could not immediately send ACT 1503 if (act_at < min_act_at && min_act_at > curTick()) 1504 bank_mask = 0; 1505 // set the bit corresponding to the available bank 1506 replaceBits(bank_mask, bank_id, bank_id, 1); 1507 min_act_at = act_at; 1508 } 1509 } 1510 } 1511 } 1512 } 1513 1514 // Determine the earliest time when the next burst can issue based 1515 // on the current busBusyUntil delay. 1516 // Offset by tRCD to correlate with ACT timing variables 1517 Tick min_cmd_at = busBusyUntil - tCL - tRCD; 1518 1519 // if we have multiple ranks and all 1520 // waiting packets are accessing a rank which was previously active 1521 // then bank_mask_same_rank will be set to a value while bank_mask will 1522 // remain 0. In this case, the function should return the value of 1523 // bank_mask_same_rank. 1524 // else if waiting packets access a rank which was previously active and 1525 // other ranks, prioritize same rank accesses that can issue B2B 1526 // Only optimize for same ranks when the command type 1527 // does not change; do not want to unnecessarily incur tWTR 1528 // 1529 // Resulting FCFS prioritization Order is: 1530 // 1) Commands that access the same rank as previous burst 1531 // and can prep the bank seamlessly. 1532 // 2) Commands (any rank) with earliest bank prep 1533 if ((bank_mask == 0) || (!switched_cmd_type && same_rank_match && 1534 min_act_at_same_rank <= min_cmd_at)) { 1535 bank_mask = bank_mask_same_rank; 1536 } 1537 1538 return bank_mask; 1539} 1540 1541DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p) 1542 : EventManager(&_memory), memory(_memory), 1543 pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), pwrStateTick(0), 1544 refreshState(REF_IDLE), refreshDueAt(0), 1545 power(_p, false), numBanksActive(0), 1546 activateEvent(*this), prechargeEvent(*this), 1547 refreshEvent(*this), powerEvent(*this) 1548{ } 1549 1550void 1551DRAMCtrl::Rank::startup(Tick ref_tick) 1552{ 1553 assert(ref_tick > curTick()); 1554 1555 pwrStateTick = curTick(); 1556 1557 // kick off the refresh, and give ourselves enough time to 1558 // precharge 1559 schedule(refreshEvent, ref_tick); 1560} 1561 1562void
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1558DRAMCtrl::Rank::checkDrainDone() 1559{ 1560 // if this rank was waiting to drain it is now able to proceed to 1561 // precharge 1562 if (refreshState == REF_DRAIN) { 1563 DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 1564 1565 refreshState = REF_PRE; 1566 1567 // hand control back to the refresh event loop 1568 schedule(refreshEvent, curTick()); 1569 } 1570} 1571 1572void 1573DRAMCtrl::Rank::processActivateEvent() 1574{ 1575 // we should transition to the active state as soon as any bank is active 1576 if (pwrState != PWR_ACT) 1577 // note that at this point numBanksActive could be back at 1578 // zero again due to a precharge scheduled in the future 1579 schedulePowerEvent(PWR_ACT, curTick()); 1580} 1581 1582void 1583DRAMCtrl::Rank::processPrechargeEvent() 1584{ 1585 // if we reached zero, then special conditions apply as we track 1586 // if all banks are precharged for the power models 1587 if (numBanksActive == 0) { 1588 // we should transition to the idle state when the last bank 1589 // is precharged 1590 schedulePowerEvent(PWR_IDLE, curTick()); 1591 } 1592} 1593 1594void 1595DRAMCtrl::Rank::processRefreshEvent() 1596{ 1597 // when first preparing the refresh, remember when it was due 1598 if (refreshState == REF_IDLE) { 1599 // remember when the refresh is due 1600 refreshDueAt = curTick(); 1601 1602 // proceed to drain 1603 refreshState = REF_DRAIN; 1604 1605 DPRINTF(DRAM, "Refresh due\n"); 1606 } 1607 1608 // let any scheduled read or write to the same rank go ahead, 1609 // after which it will 1610 // hand control back to this event loop 1611 if (refreshState == REF_DRAIN) { 1612 // if a request is at the moment being handled and this request is 1613 // accessing the current rank then wait for it to finish 1614 if ((rank == memory.activeRank) 1615 && (memory.nextReqEvent.scheduled())) { 1616 // hand control over to the request loop until it is 1617 // evaluated next 1618 DPRINTF(DRAM, "Refresh awaiting draining\n"); 1619 1620 return; 1621 } else { 1622 refreshState = REF_PRE; 1623 } 1624 } 1625 1626 // at this point, ensure that all banks are precharged 1627 if (refreshState == REF_PRE) { 1628 // precharge any active bank if we are not already in the idle 1629 // state 1630 if (pwrState != PWR_IDLE) { 1631 // at the moment, we use a precharge all even if there is 1632 // only a single bank open 1633 DPRINTF(DRAM, "Precharging all\n"); 1634 1635 // first determine when we can precharge 1636 Tick pre_at = curTick(); 1637 1638 for (auto &b : banks) { 1639 // respect both causality and any existing bank 1640 // constraints, some banks could already have a 1641 // (auto) precharge scheduled 1642 pre_at = std::max(b.preAllowedAt, pre_at); 1643 } 1644 1645 // make sure all banks per rank are precharged, and for those that 1646 // already are, update their availability 1647 Tick act_allowed_at = pre_at + memory.tRP; 1648 1649 for (auto &b : banks) { 1650 if (b.openRow != Bank::NO_ROW) { 1651 memory.prechargeBank(*this, b, pre_at, false); 1652 } else { 1653 b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 1654 b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 1655 } 1656 } 1657 1658 // precharge all banks in rank 1659 power.powerlib.doCommand(MemCommand::PREA, 0, 1660 divCeil(pre_at, memory.tCK) - 1661 memory.timeStampOffset); 1662 1663 DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 1664 divCeil(pre_at, memory.tCK) - 1665 memory.timeStampOffset, rank); 1666 } else { 1667 DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 1668 1669 // go ahead and kick the power state machine into gear if 1670 // we are already idle 1671 schedulePowerEvent(PWR_REF, curTick()); 1672 } 1673 1674 refreshState = REF_RUN; 1675 assert(numBanksActive == 0); 1676 1677 // wait for all banks to be precharged, at which point the 1678 // power state machine will transition to the idle state, and 1679 // automatically move to a refresh, at that point it will also 1680 // call this method to get the refresh event loop going again 1681 return; 1682 } 1683 1684 // last but not least we perform the actual refresh 1685 if (refreshState == REF_RUN) { 1686 // should never get here with any banks active 1687 assert(numBanksActive == 0); 1688 assert(pwrState == PWR_REF); 1689 1690 Tick ref_done_at = curTick() + memory.tRFC; 1691 1692 for (auto &b : banks) { 1693 b.actAllowedAt = ref_done_at; 1694 } 1695 1696 // at the moment this affects all ranks 1697 power.powerlib.doCommand(MemCommand::REF, 0, 1698 divCeil(curTick(), memory.tCK) - 1699 memory.timeStampOffset); 1700 1701 // at the moment sort the list of commands and update the counters 1702 // for DRAMPower libray when doing a refresh 1703 sort(power.powerlib.cmdList.begin(), 1704 power.powerlib.cmdList.end(), DRAMCtrl::sortTime); 1705 1706 // update the counters for DRAMPower, passing false to 1707 // indicate that this is not the last command in the 1708 // list. DRAMPower requires this information for the 1709 // correct calculation of the background energy at the end 1710 // of the simulation. Ideally we would want to call this 1711 // function with true once at the end of the 1712 // simulation. However, the discarded energy is extremly 1713 // small and does not effect the final results. 1714 power.powerlib.updateCounters(false); 1715 1716 // call the energy function 1717 power.powerlib.calcEnergy(); 1718 1719 // Update the stats 1720 updatePowerStats(); 1721 1722 DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 1723 memory.timeStampOffset, rank); 1724 1725 // make sure we did not wait so long that we cannot make up 1726 // for it 1727 if (refreshDueAt + memory.tREFI < ref_done_at) { 1728 fatal("Refresh was delayed so long we cannot catch up\n"); 1729 } 1730 1731 // compensate for the delay in actually performing the refresh 1732 // when scheduling the next one 1733 schedule(refreshEvent, refreshDueAt + memory.tREFI - memory.tRP); 1734 1735 assert(!powerEvent.scheduled()); 1736 1737 // move to the idle power state once the refresh is done, this 1738 // will also move the refresh state machine to the refresh 1739 // idle state 1740 schedulePowerEvent(PWR_IDLE, ref_done_at); 1741 1742 DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 1743 ref_done_at, refreshDueAt + memory.tREFI); 1744 } 1745} 1746 1747void 1748DRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 1749{ 1750 // respect causality 1751 assert(tick >= curTick()); 1752 1753 if (!powerEvent.scheduled()) { 1754 DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 1755 tick, pwr_state); 1756 1757 // insert the new transition 1758 pwrStateTrans = pwr_state; 1759 1760 schedule(powerEvent, tick); 1761 } else { 1762 panic("Scheduled power event at %llu to state %d, " 1763 "with scheduled event at %llu to %d\n", tick, pwr_state, 1764 powerEvent.when(), pwrStateTrans); 1765 } 1766} 1767 1768void 1769DRAMCtrl::Rank::processPowerEvent() 1770{ 1771 // remember where we were, and for how long 1772 Tick duration = curTick() - pwrStateTick; 1773 PowerState prev_state = pwrState; 1774 1775 // update the accounting 1776 pwrStateTime[prev_state] += duration; 1777 1778 pwrState = pwrStateTrans; 1779 pwrStateTick = curTick(); 1780 1781 if (pwrState == PWR_IDLE) { 1782 DPRINTF(DRAMState, "All banks precharged\n"); 1783 1784 // if we were refreshing, make sure we start scheduling requests again 1785 if (prev_state == PWR_REF) { 1786 DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 1787 assert(pwrState == PWR_IDLE); 1788 1789 // kick things into action again 1790 refreshState = REF_IDLE; 1791 // a request event could be already scheduled by the state 1792 // machine of the other rank 1793 if (!memory.nextReqEvent.scheduled()) 1794 schedule(memory.nextReqEvent, curTick()); 1795 } else { 1796 assert(prev_state == PWR_ACT); 1797 1798 // if we have a pending refresh, and are now moving to 1799 // the idle state, direclty transition to a refresh 1800 if (refreshState == REF_RUN) { 1801 // there should be nothing waiting at this point 1802 assert(!powerEvent.scheduled()); 1803 1804 // update the state in zero time and proceed below 1805 pwrState = PWR_REF; 1806 } 1807 } 1808 } 1809 1810 // we transition to the refresh state, let the refresh state 1811 // machine know of this state update and let it deal with the 1812 // scheduling of the next power state transition as well as the 1813 // following refresh 1814 if (pwrState == PWR_REF) { 1815 DPRINTF(DRAMState, "Refreshing\n"); 1816 // kick the refresh event loop into action again, and that 1817 // in turn will schedule a transition to the idle power 1818 // state once the refresh is done 1819 assert(refreshState == REF_RUN); 1820 processRefreshEvent(); 1821 } 1822} 1823 1824void 1825DRAMCtrl::Rank::updatePowerStats() 1826{ 1827 // Get the energy and power from DRAMPower 1828 Data::MemoryPowerModel::Energy energy = 1829 power.powerlib.getEnergy(); 1830 Data::MemoryPowerModel::Power rank_power = 1831 power.powerlib.getPower(); 1832 1833 actEnergy = energy.act_energy * memory.devicesPerRank; 1834 preEnergy = energy.pre_energy * memory.devicesPerRank; 1835 readEnergy = energy.read_energy * memory.devicesPerRank; 1836 writeEnergy = energy.write_energy * memory.devicesPerRank; 1837 refreshEnergy = energy.ref_energy * memory.devicesPerRank; 1838 actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank; 1839 preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank; 1840 totalEnergy = energy.total_energy * memory.devicesPerRank; 1841 averagePower = rank_power.average_power * memory.devicesPerRank; 1842} 1843 1844void 1845DRAMCtrl::Rank::regStats() 1846{ 1847 using namespace Stats; 1848 1849 pwrStateTime 1850 .init(5) 1851 .name(name() + ".memoryStateTime") 1852 .desc("Time in different power states"); 1853 pwrStateTime.subname(0, "IDLE"); 1854 pwrStateTime.subname(1, "REF"); 1855 pwrStateTime.subname(2, "PRE_PDN"); 1856 pwrStateTime.subname(3, "ACT"); 1857 pwrStateTime.subname(4, "ACT_PDN"); 1858 1859 actEnergy 1860 .name(name() + ".actEnergy") 1861 .desc("Energy for activate commands per rank (pJ)"); 1862 1863 preEnergy 1864 .name(name() + ".preEnergy") 1865 .desc("Energy for precharge commands per rank (pJ)"); 1866 1867 readEnergy 1868 .name(name() + ".readEnergy") 1869 .desc("Energy for read commands per rank (pJ)"); 1870 1871 writeEnergy 1872 .name(name() + ".writeEnergy") 1873 .desc("Energy for write commands per rank (pJ)"); 1874 1875 refreshEnergy 1876 .name(name() + ".refreshEnergy") 1877 .desc("Energy for refresh commands per rank (pJ)"); 1878 1879 actBackEnergy 1880 .name(name() + ".actBackEnergy") 1881 .desc("Energy for active background per rank (pJ)"); 1882 1883 preBackEnergy 1884 .name(name() + ".preBackEnergy") 1885 .desc("Energy for precharge background per rank (pJ)"); 1886 1887 totalEnergy 1888 .name(name() + ".totalEnergy") 1889 .desc("Total energy per rank (pJ)"); 1890 1891 averagePower 1892 .name(name() + ".averagePower") 1893 .desc("Core power per rank (mW)"); 1894} 1895void 1896DRAMCtrl::regStats() 1897{ 1898 using namespace Stats; 1899 1900 AbstractMemory::regStats(); 1901 1902 for (auto r : ranks) { 1903 r->regStats(); 1904 } 1905 1906 readReqs 1907 .name(name() + ".readReqs") 1908 .desc("Number of read requests accepted"); 1909 1910 writeReqs 1911 .name(name() + ".writeReqs") 1912 .desc("Number of write requests accepted"); 1913 1914 readBursts 1915 .name(name() + ".readBursts") 1916 .desc("Number of DRAM read bursts, " 1917 "including those serviced by the write queue"); 1918 1919 writeBursts 1920 .name(name() + ".writeBursts") 1921 .desc("Number of DRAM write bursts, " 1922 "including those merged in the write queue"); 1923 1924 servicedByWrQ 1925 .name(name() + ".servicedByWrQ") 1926 .desc("Number of DRAM read bursts serviced by the write queue"); 1927 1928 mergedWrBursts 1929 .name(name() + ".mergedWrBursts") 1930 .desc("Number of DRAM write bursts merged with an existing one"); 1931 1932 neitherReadNorWrite 1933 .name(name() + ".neitherReadNorWriteReqs") 1934 .desc("Number of requests that are neither read nor write"); 1935 1936 perBankRdBursts 1937 .init(banksPerRank * ranksPerChannel) 1938 .name(name() + ".perBankRdBursts") 1939 .desc("Per bank write bursts"); 1940 1941 perBankWrBursts 1942 .init(banksPerRank * ranksPerChannel) 1943 .name(name() + ".perBankWrBursts") 1944 .desc("Per bank write bursts"); 1945 1946 avgRdQLen 1947 .name(name() + ".avgRdQLen") 1948 .desc("Average read queue length when enqueuing") 1949 .precision(2); 1950 1951 avgWrQLen 1952 .name(name() + ".avgWrQLen") 1953 .desc("Average write queue length when enqueuing") 1954 .precision(2); 1955 1956 totQLat 1957 .name(name() + ".totQLat") 1958 .desc("Total ticks spent queuing"); 1959 1960 totBusLat 1961 .name(name() + ".totBusLat") 1962 .desc("Total ticks spent in databus transfers"); 1963 1964 totMemAccLat 1965 .name(name() + ".totMemAccLat") 1966 .desc("Total ticks spent from burst creation until serviced " 1967 "by the DRAM"); 1968 1969 avgQLat 1970 .name(name() + ".avgQLat") 1971 .desc("Average queueing delay per DRAM burst") 1972 .precision(2); 1973 1974 avgQLat = totQLat / (readBursts - servicedByWrQ); 1975 1976 avgBusLat 1977 .name(name() + ".avgBusLat") 1978 .desc("Average bus latency per DRAM burst") 1979 .precision(2); 1980 1981 avgBusLat = totBusLat / (readBursts - servicedByWrQ); 1982 1983 avgMemAccLat 1984 .name(name() + ".avgMemAccLat") 1985 .desc("Average memory access latency per DRAM burst") 1986 .precision(2); 1987 1988 avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 1989 1990 numRdRetry 1991 .name(name() + ".numRdRetry") 1992 .desc("Number of times read queue was full causing retry"); 1993 1994 numWrRetry 1995 .name(name() + ".numWrRetry") 1996 .desc("Number of times write queue was full causing retry"); 1997 1998 readRowHits 1999 .name(name() + ".readRowHits") 2000 .desc("Number of row buffer hits during reads"); 2001 2002 writeRowHits 2003 .name(name() + ".writeRowHits") 2004 .desc("Number of row buffer hits during writes"); 2005 2006 readRowHitRate 2007 .name(name() + ".readRowHitRate") 2008 .desc("Row buffer hit rate for reads") 2009 .precision(2); 2010 2011 readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 2012 2013 writeRowHitRate 2014 .name(name() + ".writeRowHitRate") 2015 .desc("Row buffer hit rate for writes") 2016 .precision(2); 2017 2018 writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 2019 2020 readPktSize 2021 .init(ceilLog2(burstSize) + 1) 2022 .name(name() + ".readPktSize") 2023 .desc("Read request sizes (log2)"); 2024 2025 writePktSize 2026 .init(ceilLog2(burstSize) + 1) 2027 .name(name() + ".writePktSize") 2028 .desc("Write request sizes (log2)"); 2029 2030 rdQLenPdf 2031 .init(readBufferSize) 2032 .name(name() + ".rdQLenPdf") 2033 .desc("What read queue length does an incoming req see"); 2034 2035 wrQLenPdf 2036 .init(writeBufferSize) 2037 .name(name() + ".wrQLenPdf") 2038 .desc("What write queue length does an incoming req see"); 2039 2040 bytesPerActivate 2041 .init(maxAccessesPerRow) 2042 .name(name() + ".bytesPerActivate") 2043 .desc("Bytes accessed per row activation") 2044 .flags(nozero); 2045 2046 rdPerTurnAround 2047 .init(readBufferSize) 2048 .name(name() + ".rdPerTurnAround") 2049 .desc("Reads before turning the bus around for writes") 2050 .flags(nozero); 2051 2052 wrPerTurnAround 2053 .init(writeBufferSize) 2054 .name(name() + ".wrPerTurnAround") 2055 .desc("Writes before turning the bus around for reads") 2056 .flags(nozero); 2057 2058 bytesReadDRAM 2059 .name(name() + ".bytesReadDRAM") 2060 .desc("Total number of bytes read from DRAM"); 2061 2062 bytesReadWrQ 2063 .name(name() + ".bytesReadWrQ") 2064 .desc("Total number of bytes read from write queue"); 2065 2066 bytesWritten 2067 .name(name() + ".bytesWritten") 2068 .desc("Total number of bytes written to DRAM"); 2069 2070 bytesReadSys 2071 .name(name() + ".bytesReadSys") 2072 .desc("Total read bytes from the system interface side"); 2073 2074 bytesWrittenSys 2075 .name(name() + ".bytesWrittenSys") 2076 .desc("Total written bytes from the system interface side"); 2077 2078 avgRdBW 2079 .name(name() + ".avgRdBW") 2080 .desc("Average DRAM read bandwidth in MiByte/s") 2081 .precision(2); 2082 2083 avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 2084 2085 avgWrBW 2086 .name(name() + ".avgWrBW") 2087 .desc("Average achieved write bandwidth in MiByte/s") 2088 .precision(2); 2089 2090 avgWrBW = (bytesWritten / 1000000) / simSeconds; 2091 2092 avgRdBWSys 2093 .name(name() + ".avgRdBWSys") 2094 .desc("Average system read bandwidth in MiByte/s") 2095 .precision(2); 2096 2097 avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 2098 2099 avgWrBWSys 2100 .name(name() + ".avgWrBWSys") 2101 .desc("Average system write bandwidth in MiByte/s") 2102 .precision(2); 2103 2104 avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 2105 2106 peakBW 2107 .name(name() + ".peakBW") 2108 .desc("Theoretical peak bandwidth in MiByte/s") 2109 .precision(2); 2110 2111 peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 2112 2113 busUtil 2114 .name(name() + ".busUtil") 2115 .desc("Data bus utilization in percentage") 2116 .precision(2); 2117 busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 2118 2119 totGap 2120 .name(name() + ".totGap") 2121 .desc("Total gap between requests"); 2122 2123 avgGap 2124 .name(name() + ".avgGap") 2125 .desc("Average gap between requests") 2126 .precision(2); 2127 2128 avgGap = totGap / (readReqs + writeReqs); 2129 2130 // Stats for DRAM Power calculation based on Micron datasheet 2131 busUtilRead 2132 .name(name() + ".busUtilRead") 2133 .desc("Data bus utilization in percentage for reads") 2134 .precision(2); 2135 2136 busUtilRead = avgRdBW / peakBW * 100; 2137 2138 busUtilWrite 2139 .name(name() + ".busUtilWrite") 2140 .desc("Data bus utilization in percentage for writes") 2141 .precision(2); 2142 2143 busUtilWrite = avgWrBW / peakBW * 100; 2144 2145 pageHitRate 2146 .name(name() + ".pageHitRate") 2147 .desc("Row buffer hit rate, read and write combined") 2148 .precision(2); 2149 2150 pageHitRate = (writeRowHits + readRowHits) / 2151 (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 2152} 2153 2154void 2155DRAMCtrl::recvFunctional(PacketPtr pkt) 2156{ 2157 // rely on the abstract memory 2158 functionalAccess(pkt); 2159} 2160 2161BaseSlavePort& 2162DRAMCtrl::getSlavePort(const string &if_name, PortID idx) 2163{ 2164 if (if_name != "port") { 2165 return MemObject::getSlavePort(if_name, idx); 2166 } else { 2167 return port; 2168 } 2169} 2170 2171unsigned int 2172DRAMCtrl::drain(DrainManager *dm) 2173{ 2174 unsigned int count = port.drain(dm); 2175 2176 // if there is anything in any of our internal queues, keep track 2177 // of that as well 2178 if (!(writeQueue.empty() && readQueue.empty() && 2179 respQueue.empty())) { 2180 DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 2181 " resp: %d\n", writeQueue.size(), readQueue.size(), 2182 respQueue.size()); 2183 ++count; 2184 drainManager = dm; 2185 2186 // the only part that is not drained automatically over time 2187 // is the write queue, thus kick things into action if needed 2188 if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 2189 schedule(nextReqEvent, curTick()); 2190 } 2191 } 2192 2193 if (count) 2194 setDrainState(Drainable::Draining); 2195 else 2196 setDrainState(Drainable::Drained); 2197 return count; 2198} 2199
| 1569DRAMCtrl::Rank::checkDrainDone() 1570{ 1571 // if this rank was waiting to drain it is now able to proceed to 1572 // precharge 1573 if (refreshState == REF_DRAIN) { 1574 DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 1575 1576 refreshState = REF_PRE; 1577 1578 // hand control back to the refresh event loop 1579 schedule(refreshEvent, curTick()); 1580 } 1581} 1582 1583void 1584DRAMCtrl::Rank::processActivateEvent() 1585{ 1586 // we should transition to the active state as soon as any bank is active 1587 if (pwrState != PWR_ACT) 1588 // note that at this point numBanksActive could be back at 1589 // zero again due to a precharge scheduled in the future 1590 schedulePowerEvent(PWR_ACT, curTick()); 1591} 1592 1593void 1594DRAMCtrl::Rank::processPrechargeEvent() 1595{ 1596 // if we reached zero, then special conditions apply as we track 1597 // if all banks are precharged for the power models 1598 if (numBanksActive == 0) { 1599 // we should transition to the idle state when the last bank 1600 // is precharged 1601 schedulePowerEvent(PWR_IDLE, curTick()); 1602 } 1603} 1604 1605void 1606DRAMCtrl::Rank::processRefreshEvent() 1607{ 1608 // when first preparing the refresh, remember when it was due 1609 if (refreshState == REF_IDLE) { 1610 // remember when the refresh is due 1611 refreshDueAt = curTick(); 1612 1613 // proceed to drain 1614 refreshState = REF_DRAIN; 1615 1616 DPRINTF(DRAM, "Refresh due\n"); 1617 } 1618 1619 // let any scheduled read or write to the same rank go ahead, 1620 // after which it will 1621 // hand control back to this event loop 1622 if (refreshState == REF_DRAIN) { 1623 // if a request is at the moment being handled and this request is 1624 // accessing the current rank then wait for it to finish 1625 if ((rank == memory.activeRank) 1626 && (memory.nextReqEvent.scheduled())) { 1627 // hand control over to the request loop until it is 1628 // evaluated next 1629 DPRINTF(DRAM, "Refresh awaiting draining\n"); 1630 1631 return; 1632 } else { 1633 refreshState = REF_PRE; 1634 } 1635 } 1636 1637 // at this point, ensure that all banks are precharged 1638 if (refreshState == REF_PRE) { 1639 // precharge any active bank if we are not already in the idle 1640 // state 1641 if (pwrState != PWR_IDLE) { 1642 // at the moment, we use a precharge all even if there is 1643 // only a single bank open 1644 DPRINTF(DRAM, "Precharging all\n"); 1645 1646 // first determine when we can precharge 1647 Tick pre_at = curTick(); 1648 1649 for (auto &b : banks) { 1650 // respect both causality and any existing bank 1651 // constraints, some banks could already have a 1652 // (auto) precharge scheduled 1653 pre_at = std::max(b.preAllowedAt, pre_at); 1654 } 1655 1656 // make sure all banks per rank are precharged, and for those that 1657 // already are, update their availability 1658 Tick act_allowed_at = pre_at + memory.tRP; 1659 1660 for (auto &b : banks) { 1661 if (b.openRow != Bank::NO_ROW) { 1662 memory.prechargeBank(*this, b, pre_at, false); 1663 } else { 1664 b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 1665 b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 1666 } 1667 } 1668 1669 // precharge all banks in rank 1670 power.powerlib.doCommand(MemCommand::PREA, 0, 1671 divCeil(pre_at, memory.tCK) - 1672 memory.timeStampOffset); 1673 1674 DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 1675 divCeil(pre_at, memory.tCK) - 1676 memory.timeStampOffset, rank); 1677 } else { 1678 DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 1679 1680 // go ahead and kick the power state machine into gear if 1681 // we are already idle 1682 schedulePowerEvent(PWR_REF, curTick()); 1683 } 1684 1685 refreshState = REF_RUN; 1686 assert(numBanksActive == 0); 1687 1688 // wait for all banks to be precharged, at which point the 1689 // power state machine will transition to the idle state, and 1690 // automatically move to a refresh, at that point it will also 1691 // call this method to get the refresh event loop going again 1692 return; 1693 } 1694 1695 // last but not least we perform the actual refresh 1696 if (refreshState == REF_RUN) { 1697 // should never get here with any banks active 1698 assert(numBanksActive == 0); 1699 assert(pwrState == PWR_REF); 1700 1701 Tick ref_done_at = curTick() + memory.tRFC; 1702 1703 for (auto &b : banks) { 1704 b.actAllowedAt = ref_done_at; 1705 } 1706 1707 // at the moment this affects all ranks 1708 power.powerlib.doCommand(MemCommand::REF, 0, 1709 divCeil(curTick(), memory.tCK) - 1710 memory.timeStampOffset); 1711 1712 // at the moment sort the list of commands and update the counters 1713 // for DRAMPower libray when doing a refresh 1714 sort(power.powerlib.cmdList.begin(), 1715 power.powerlib.cmdList.end(), DRAMCtrl::sortTime); 1716 1717 // update the counters for DRAMPower, passing false to 1718 // indicate that this is not the last command in the 1719 // list. DRAMPower requires this information for the 1720 // correct calculation of the background energy at the end 1721 // of the simulation. Ideally we would want to call this 1722 // function with true once at the end of the 1723 // simulation. However, the discarded energy is extremly 1724 // small and does not effect the final results. 1725 power.powerlib.updateCounters(false); 1726 1727 // call the energy function 1728 power.powerlib.calcEnergy(); 1729 1730 // Update the stats 1731 updatePowerStats(); 1732 1733 DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 1734 memory.timeStampOffset, rank); 1735 1736 // make sure we did not wait so long that we cannot make up 1737 // for it 1738 if (refreshDueAt + memory.tREFI < ref_done_at) { 1739 fatal("Refresh was delayed so long we cannot catch up\n"); 1740 } 1741 1742 // compensate for the delay in actually performing the refresh 1743 // when scheduling the next one 1744 schedule(refreshEvent, refreshDueAt + memory.tREFI - memory.tRP); 1745 1746 assert(!powerEvent.scheduled()); 1747 1748 // move to the idle power state once the refresh is done, this 1749 // will also move the refresh state machine to the refresh 1750 // idle state 1751 schedulePowerEvent(PWR_IDLE, ref_done_at); 1752 1753 DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n", 1754 ref_done_at, refreshDueAt + memory.tREFI); 1755 } 1756} 1757 1758void 1759DRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 1760{ 1761 // respect causality 1762 assert(tick >= curTick()); 1763 1764 if (!powerEvent.scheduled()) { 1765 DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 1766 tick, pwr_state); 1767 1768 // insert the new transition 1769 pwrStateTrans = pwr_state; 1770 1771 schedule(powerEvent, tick); 1772 } else { 1773 panic("Scheduled power event at %llu to state %d, " 1774 "with scheduled event at %llu to %d\n", tick, pwr_state, 1775 powerEvent.when(), pwrStateTrans); 1776 } 1777} 1778 1779void 1780DRAMCtrl::Rank::processPowerEvent() 1781{ 1782 // remember where we were, and for how long 1783 Tick duration = curTick() - pwrStateTick; 1784 PowerState prev_state = pwrState; 1785 1786 // update the accounting 1787 pwrStateTime[prev_state] += duration; 1788 1789 pwrState = pwrStateTrans; 1790 pwrStateTick = curTick(); 1791 1792 if (pwrState == PWR_IDLE) { 1793 DPRINTF(DRAMState, "All banks precharged\n"); 1794 1795 // if we were refreshing, make sure we start scheduling requests again 1796 if (prev_state == PWR_REF) { 1797 DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 1798 assert(pwrState == PWR_IDLE); 1799 1800 // kick things into action again 1801 refreshState = REF_IDLE; 1802 // a request event could be already scheduled by the state 1803 // machine of the other rank 1804 if (!memory.nextReqEvent.scheduled()) 1805 schedule(memory.nextReqEvent, curTick()); 1806 } else { 1807 assert(prev_state == PWR_ACT); 1808 1809 // if we have a pending refresh, and are now moving to 1810 // the idle state, direclty transition to a refresh 1811 if (refreshState == REF_RUN) { 1812 // there should be nothing waiting at this point 1813 assert(!powerEvent.scheduled()); 1814 1815 // update the state in zero time and proceed below 1816 pwrState = PWR_REF; 1817 } 1818 } 1819 } 1820 1821 // we transition to the refresh state, let the refresh state 1822 // machine know of this state update and let it deal with the 1823 // scheduling of the next power state transition as well as the 1824 // following refresh 1825 if (pwrState == PWR_REF) { 1826 DPRINTF(DRAMState, "Refreshing\n"); 1827 // kick the refresh event loop into action again, and that 1828 // in turn will schedule a transition to the idle power 1829 // state once the refresh is done 1830 assert(refreshState == REF_RUN); 1831 processRefreshEvent(); 1832 } 1833} 1834 1835void 1836DRAMCtrl::Rank::updatePowerStats() 1837{ 1838 // Get the energy and power from DRAMPower 1839 Data::MemoryPowerModel::Energy energy = 1840 power.powerlib.getEnergy(); 1841 Data::MemoryPowerModel::Power rank_power = 1842 power.powerlib.getPower(); 1843 1844 actEnergy = energy.act_energy * memory.devicesPerRank; 1845 preEnergy = energy.pre_energy * memory.devicesPerRank; 1846 readEnergy = energy.read_energy * memory.devicesPerRank; 1847 writeEnergy = energy.write_energy * memory.devicesPerRank; 1848 refreshEnergy = energy.ref_energy * memory.devicesPerRank; 1849 actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank; 1850 preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank; 1851 totalEnergy = energy.total_energy * memory.devicesPerRank; 1852 averagePower = rank_power.average_power * memory.devicesPerRank; 1853} 1854 1855void 1856DRAMCtrl::Rank::regStats() 1857{ 1858 using namespace Stats; 1859 1860 pwrStateTime 1861 .init(5) 1862 .name(name() + ".memoryStateTime") 1863 .desc("Time in different power states"); 1864 pwrStateTime.subname(0, "IDLE"); 1865 pwrStateTime.subname(1, "REF"); 1866 pwrStateTime.subname(2, "PRE_PDN"); 1867 pwrStateTime.subname(3, "ACT"); 1868 pwrStateTime.subname(4, "ACT_PDN"); 1869 1870 actEnergy 1871 .name(name() + ".actEnergy") 1872 .desc("Energy for activate commands per rank (pJ)"); 1873 1874 preEnergy 1875 .name(name() + ".preEnergy") 1876 .desc("Energy for precharge commands per rank (pJ)"); 1877 1878 readEnergy 1879 .name(name() + ".readEnergy") 1880 .desc("Energy for read commands per rank (pJ)"); 1881 1882 writeEnergy 1883 .name(name() + ".writeEnergy") 1884 .desc("Energy for write commands per rank (pJ)"); 1885 1886 refreshEnergy 1887 .name(name() + ".refreshEnergy") 1888 .desc("Energy for refresh commands per rank (pJ)"); 1889 1890 actBackEnergy 1891 .name(name() + ".actBackEnergy") 1892 .desc("Energy for active background per rank (pJ)"); 1893 1894 preBackEnergy 1895 .name(name() + ".preBackEnergy") 1896 .desc("Energy for precharge background per rank (pJ)"); 1897 1898 totalEnergy 1899 .name(name() + ".totalEnergy") 1900 .desc("Total energy per rank (pJ)"); 1901 1902 averagePower 1903 .name(name() + ".averagePower") 1904 .desc("Core power per rank (mW)"); 1905} 1906void 1907DRAMCtrl::regStats() 1908{ 1909 using namespace Stats; 1910 1911 AbstractMemory::regStats(); 1912 1913 for (auto r : ranks) { 1914 r->regStats(); 1915 } 1916 1917 readReqs 1918 .name(name() + ".readReqs") 1919 .desc("Number of read requests accepted"); 1920 1921 writeReqs 1922 .name(name() + ".writeReqs") 1923 .desc("Number of write requests accepted"); 1924 1925 readBursts 1926 .name(name() + ".readBursts") 1927 .desc("Number of DRAM read bursts, " 1928 "including those serviced by the write queue"); 1929 1930 writeBursts 1931 .name(name() + ".writeBursts") 1932 .desc("Number of DRAM write bursts, " 1933 "including those merged in the write queue"); 1934 1935 servicedByWrQ 1936 .name(name() + ".servicedByWrQ") 1937 .desc("Number of DRAM read bursts serviced by the write queue"); 1938 1939 mergedWrBursts 1940 .name(name() + ".mergedWrBursts") 1941 .desc("Number of DRAM write bursts merged with an existing one"); 1942 1943 neitherReadNorWrite 1944 .name(name() + ".neitherReadNorWriteReqs") 1945 .desc("Number of requests that are neither read nor write"); 1946 1947 perBankRdBursts 1948 .init(banksPerRank * ranksPerChannel) 1949 .name(name() + ".perBankRdBursts") 1950 .desc("Per bank write bursts"); 1951 1952 perBankWrBursts 1953 .init(banksPerRank * ranksPerChannel) 1954 .name(name() + ".perBankWrBursts") 1955 .desc("Per bank write bursts"); 1956 1957 avgRdQLen 1958 .name(name() + ".avgRdQLen") 1959 .desc("Average read queue length when enqueuing") 1960 .precision(2); 1961 1962 avgWrQLen 1963 .name(name() + ".avgWrQLen") 1964 .desc("Average write queue length when enqueuing") 1965 .precision(2); 1966 1967 totQLat 1968 .name(name() + ".totQLat") 1969 .desc("Total ticks spent queuing"); 1970 1971 totBusLat 1972 .name(name() + ".totBusLat") 1973 .desc("Total ticks spent in databus transfers"); 1974 1975 totMemAccLat 1976 .name(name() + ".totMemAccLat") 1977 .desc("Total ticks spent from burst creation until serviced " 1978 "by the DRAM"); 1979 1980 avgQLat 1981 .name(name() + ".avgQLat") 1982 .desc("Average queueing delay per DRAM burst") 1983 .precision(2); 1984 1985 avgQLat = totQLat / (readBursts - servicedByWrQ); 1986 1987 avgBusLat 1988 .name(name() + ".avgBusLat") 1989 .desc("Average bus latency per DRAM burst") 1990 .precision(2); 1991 1992 avgBusLat = totBusLat / (readBursts - servicedByWrQ); 1993 1994 avgMemAccLat 1995 .name(name() + ".avgMemAccLat") 1996 .desc("Average memory access latency per DRAM burst") 1997 .precision(2); 1998 1999 avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 2000 2001 numRdRetry 2002 .name(name() + ".numRdRetry") 2003 .desc("Number of times read queue was full causing retry"); 2004 2005 numWrRetry 2006 .name(name() + ".numWrRetry") 2007 .desc("Number of times write queue was full causing retry"); 2008 2009 readRowHits 2010 .name(name() + ".readRowHits") 2011 .desc("Number of row buffer hits during reads"); 2012 2013 writeRowHits 2014 .name(name() + ".writeRowHits") 2015 .desc("Number of row buffer hits during writes"); 2016 2017 readRowHitRate 2018 .name(name() + ".readRowHitRate") 2019 .desc("Row buffer hit rate for reads") 2020 .precision(2); 2021 2022 readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 2023 2024 writeRowHitRate 2025 .name(name() + ".writeRowHitRate") 2026 .desc("Row buffer hit rate for writes") 2027 .precision(2); 2028 2029 writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 2030 2031 readPktSize 2032 .init(ceilLog2(burstSize) + 1) 2033 .name(name() + ".readPktSize") 2034 .desc("Read request sizes (log2)"); 2035 2036 writePktSize 2037 .init(ceilLog2(burstSize) + 1) 2038 .name(name() + ".writePktSize") 2039 .desc("Write request sizes (log2)"); 2040 2041 rdQLenPdf 2042 .init(readBufferSize) 2043 .name(name() + ".rdQLenPdf") 2044 .desc("What read queue length does an incoming req see"); 2045 2046 wrQLenPdf 2047 .init(writeBufferSize) 2048 .name(name() + ".wrQLenPdf") 2049 .desc("What write queue length does an incoming req see"); 2050 2051 bytesPerActivate 2052 .init(maxAccessesPerRow) 2053 .name(name() + ".bytesPerActivate") 2054 .desc("Bytes accessed per row activation") 2055 .flags(nozero); 2056 2057 rdPerTurnAround 2058 .init(readBufferSize) 2059 .name(name() + ".rdPerTurnAround") 2060 .desc("Reads before turning the bus around for writes") 2061 .flags(nozero); 2062 2063 wrPerTurnAround 2064 .init(writeBufferSize) 2065 .name(name() + ".wrPerTurnAround") 2066 .desc("Writes before turning the bus around for reads") 2067 .flags(nozero); 2068 2069 bytesReadDRAM 2070 .name(name() + ".bytesReadDRAM") 2071 .desc("Total number of bytes read from DRAM"); 2072 2073 bytesReadWrQ 2074 .name(name() + ".bytesReadWrQ") 2075 .desc("Total number of bytes read from write queue"); 2076 2077 bytesWritten 2078 .name(name() + ".bytesWritten") 2079 .desc("Total number of bytes written to DRAM"); 2080 2081 bytesReadSys 2082 .name(name() + ".bytesReadSys") 2083 .desc("Total read bytes from the system interface side"); 2084 2085 bytesWrittenSys 2086 .name(name() + ".bytesWrittenSys") 2087 .desc("Total written bytes from the system interface side"); 2088 2089 avgRdBW 2090 .name(name() + ".avgRdBW") 2091 .desc("Average DRAM read bandwidth in MiByte/s") 2092 .precision(2); 2093 2094 avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 2095 2096 avgWrBW 2097 .name(name() + ".avgWrBW") 2098 .desc("Average achieved write bandwidth in MiByte/s") 2099 .precision(2); 2100 2101 avgWrBW = (bytesWritten / 1000000) / simSeconds; 2102 2103 avgRdBWSys 2104 .name(name() + ".avgRdBWSys") 2105 .desc("Average system read bandwidth in MiByte/s") 2106 .precision(2); 2107 2108 avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 2109 2110 avgWrBWSys 2111 .name(name() + ".avgWrBWSys") 2112 .desc("Average system write bandwidth in MiByte/s") 2113 .precision(2); 2114 2115 avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 2116 2117 peakBW 2118 .name(name() + ".peakBW") 2119 .desc("Theoretical peak bandwidth in MiByte/s") 2120 .precision(2); 2121 2122 peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 2123 2124 busUtil 2125 .name(name() + ".busUtil") 2126 .desc("Data bus utilization in percentage") 2127 .precision(2); 2128 busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 2129 2130 totGap 2131 .name(name() + ".totGap") 2132 .desc("Total gap between requests"); 2133 2134 avgGap 2135 .name(name() + ".avgGap") 2136 .desc("Average gap between requests") 2137 .precision(2); 2138 2139 avgGap = totGap / (readReqs + writeReqs); 2140 2141 // Stats for DRAM Power calculation based on Micron datasheet 2142 busUtilRead 2143 .name(name() + ".busUtilRead") 2144 .desc("Data bus utilization in percentage for reads") 2145 .precision(2); 2146 2147 busUtilRead = avgRdBW / peakBW * 100; 2148 2149 busUtilWrite 2150 .name(name() + ".busUtilWrite") 2151 .desc("Data bus utilization in percentage for writes") 2152 .precision(2); 2153 2154 busUtilWrite = avgWrBW / peakBW * 100; 2155 2156 pageHitRate 2157 .name(name() + ".pageHitRate") 2158 .desc("Row buffer hit rate, read and write combined") 2159 .precision(2); 2160 2161 pageHitRate = (writeRowHits + readRowHits) / 2162 (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 2163} 2164 2165void 2166DRAMCtrl::recvFunctional(PacketPtr pkt) 2167{ 2168 // rely on the abstract memory 2169 functionalAccess(pkt); 2170} 2171 2172BaseSlavePort& 2173DRAMCtrl::getSlavePort(const string &if_name, PortID idx) 2174{ 2175 if (if_name != "port") { 2176 return MemObject::getSlavePort(if_name, idx); 2177 } else { 2178 return port; 2179 } 2180} 2181 2182unsigned int 2183DRAMCtrl::drain(DrainManager *dm) 2184{ 2185 unsigned int count = port.drain(dm); 2186 2187 // if there is anything in any of our internal queues, keep track 2188 // of that as well 2189 if (!(writeQueue.empty() && readQueue.empty() && 2190 respQueue.empty())) { 2191 DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 2192 " resp: %d\n", writeQueue.size(), readQueue.size(), 2193 respQueue.size()); 2194 ++count; 2195 drainManager = dm; 2196 2197 // the only part that is not drained automatically over time 2198 // is the write queue, thus kick things into action if needed 2199 if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 2200 schedule(nextReqEvent, curTick()); 2201 } 2202 } 2203 2204 if (count) 2205 setDrainState(Drainable::Draining); 2206 else 2207 setDrainState(Drainable::Drained); 2208 return count; 2209} 2210
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