1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 * Omar Naji
44 */
45
46#include "base/bitfield.hh"
47#include "base/trace.hh"
48#include "debug/DRAM.hh"
49#include "debug/DRAMPower.hh"
50#include "debug/DRAMState.hh"
51#include "debug/Drain.hh"
52#include "mem/dram_ctrl.hh"
53#include "sim/system.hh"
54
55using namespace std;
56using namespace Data;
57
58DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
59 AbstractMemory(p),
60 port(name() + ".port", *this), isTimingMode(false),
61 retryRdReq(false), retryWrReq(false),
62 busState(READ),
63 nextReqEvent(this), respondEvent(this),
64 deviceSize(p->device_size),
65 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
66 deviceRowBufferSize(p->device_rowbuffer_size),
67 devicesPerRank(p->devices_per_rank),
68 burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8),
69 rowBufferSize(devicesPerRank * deviceRowBufferSize),
70 columnsPerRowBuffer(rowBufferSize / burstSize),

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476
477 assert(!readQueueFull(1));
478 rdQLenPdf[readQueue.size() + respQueue.size()]++;
479
480 DPRINTF(DRAM, "Adding to read queue\n");
481
482 readQueue.push_back(dram_pkt);
483
484 // Update stats
485 avgRdQLen = readQueue.size() + respQueue.size();
486 }
487
488 // Starting address of next dram pkt (aligend to burstSize boundary)
489 addr = (addr | (burstSize - 1)) + 1;
490 }
491

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539 DPRINTF(DRAM, "Adding to write queue\n");
540
541 writeQueue.push_back(dram_pkt);
542 isInWriteQueue.insert(burstAlign(addr));
543 assert(writeQueue.size() == isInWriteQueue.size());
544
545 // Update stats
546 avgWrQLen = writeQueue.size();
547 } else {
548 DPRINTF(DRAM, "Merging write burst with existing queue entry\n");
549
550 // keep track of the fact that this burst effectively
551 // disappeared as it was merged with an existing one
552 mergedWrBursts++;
553 }
554

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651void
652DRAMCtrl::processRespondEvent()
653{
654 DPRINTF(DRAM,
655 "processRespondEvent(): Some req has reached its readyTime\n");
656
657 DRAMPacket* dram_pkt = respQueue.front();
658
659 if (dram_pkt->burstHelper) {
660 // it is a split packet
661 dram_pkt->burstHelper->burstsServiced++;
662 if (dram_pkt->burstHelper->burstsServiced ==
663 dram_pkt->burstHelper->burstCount) {
664 // we have now serviced all children packets of a system packet
665 // so we can now respond to the requester
666 // @todo we probably want to have a different front end and back

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1007 timeStampOffset, bank.bank, rank_ref.rank);
1008 }
1009 // if we look at the current number of active banks we might be
1010 // tempted to think the DRAM is now idle, however this can be
1011 // undone by an activate that is scheduled to happen before we
1012 // would have reached the idle state, so schedule an event and
1013 // rather check once we actually make it to the point in time when
1014 // the (last) precharge takes place
1015 if (!rank_ref.prechargeEvent.scheduled())
1016 schedule(rank_ref.prechargeEvent, pre_done_at);
1017 else if (rank_ref.prechargeEvent.when() < pre_done_at)
1018 reschedule(rank_ref.prechargeEvent, pre_done_at);
1019}
1020
1021void
1022DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
1023{
1024 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
1025 dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row);
1026
1027 // get the rank
1028 Rank& rank = dram_pkt->rankRef;
1029
1030 // get the bank
1031 Bank& bank = dram_pkt->bankRef;
1032
1033 // for the state we need to track if it is a row hit or not
1034 bool row_hit = true;
1035
1036 // respect any constraints on the command (e.g. tRCD or tCCD)
1037 Tick cmd_at = std::max(bank.colAllowedAt, curTick());

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1224}
1225
1226void
1227DRAMCtrl::processNextReqEvent()
1228{
1229 int busyRanks = 0;
1230 for (auto r : ranks) {
1231 if (!r->isAvailable()) {
1232 // rank is busy refreshing
1233 busyRanks++;
1234
1235 // let the rank know that if it was waiting to drain, it
1236 // is now done and ready to proceed
1237 r->checkDrainDone();
1238 }
1239 }
1240
1241 if (busyRanks == ranksPerChannel) {
1242 // if all ranks are refreshing wait for them to finish
1243 // and stall this state machine without taking any further
1244 // action, and do not schedule a new nextReqEvent
1245 return;
1246 }
1247
1248 // pre-emptively set to false. Overwrite if in READ_TO_WRITE
1249 // or WRITE_TO_READ state
1250 bool switched_cmd_type = false;
1251 if (busState == READ_TO_WRITE) {
1252 DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
1253 "waiting\n", readsThisTime, readQueue.size());
1254
1255 // sample and reset the read-related stats as we are now
1256 // transitioning to writes, and all reads are done
1257 rdPerTurnAround.sample(readsThisTime);
1258 readsThisTime = 0;
1259
1260 // now proceed to do the actual writes
1261 busState = WRITE;
1262 switched_cmd_type = true;
1263 } else if (busState == WRITE_TO_READ) {
1264 DPRINTF(DRAM, "Switching to reads after %d writes with %d writes "
1265 "waiting\n", writesThisTime, writeQueue.size());
1266
1267 wrPerTurnAround.sample(writesThisTime);
1268 writesThisTime = 0;
1269
1270 busState = READ;
1271 switched_cmd_type = true;
1272 }
1273
1274 // when we get here it is either a read or a write
1275 if (busState == READ) {
1276
1277 // track if we should switch or not
1278 bool switch_to_writes = false;
1279

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1318 // which are above the required threshold. However, to
1319 // avoid adding more complexity to the code, return and wait
1320 // for a refresh event to kick things into action again.
1321 if (!found_read)
1322 return;
1323
1324 DRAMPacket* dram_pkt = readQueue.front();
1325 assert(dram_pkt->rankRef.isAvailable());
1326 // here we get a bit creative and shift the bus busy time not
1327 // just the tWTR, but also a CAS latency to capture the fact
1328 // that we are allowed to prepare a new bank, but not issue a
1329 // read command until after tWTR, in essence we capture a
1330 // bubble on the data bus that is tWTR + tCL
1331 if (switched_cmd_type && dram_pkt->rank == activeRank) {
1332 busBusyUntil += tWTR + tCL;
1333 }
1334
1335 doDRAMAccess(dram_pkt);
1336
1337 // At this point we're done dealing with the request
1338 readQueue.pop_front();
1339
1340 // sanity check
1341 assert(dram_pkt->size <= burstSize);
1342 assert(dram_pkt->readyTime >= curTick());
1343
1344 // Insert into response queue. It will be sent back to the
1345 // requestor at its readyTime
1346 if (respQueue.empty()) {
1347 assert(!respondEvent.scheduled());

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1359 }
1360 }
1361
1362 // switching to writes, either because the read queue is empty
1363 // and the writes have passed the low threshold (or we are
1364 // draining), or because the writes hit the hight threshold
1365 if (switch_to_writes) {
1366 // transition to writing
1367 busState = READ_TO_WRITE;
1368 }
1369 } else {
1370 // bool to check if write to free rank is found
1371 bool found_write = false;
1372
1373 // If we are changing command type, incorporate the minimum
1374 // bus turnaround delay
1375 found_write = chooseNext(writeQueue,

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1393 // applied to colAllowedAt
1394 if (switched_cmd_type && dram_pkt->rank == activeRank) {
1395 busBusyUntil += tRTW;
1396 }
1397
1398 doDRAMAccess(dram_pkt);
1399
1400 writeQueue.pop_front();
1401 isInWriteQueue.erase(burstAlign(dram_pkt->addr));
1402 delete dram_pkt;
1403
1404 // If we emptied the write queue, or got sufficiently below the
1405 // threshold (using the minWritesPerSwitch as the hysteresis) and
1406 // are not draining, or we have reads waiting and have done enough
1407 // writes, then switch to reads.
1408 if (writeQueue.empty() ||
1409 (writeQueue.size() + minWritesPerSwitch < writeLowThreshold &&
1410 drainState() != DrainState::Draining) ||
1411 (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) {
1412 // turn the bus back around for reads again
1413 busState = WRITE_TO_READ;
1414
1415 // note that the we switch back to reads also in the idle
1416 // case, which eventually will check for any draining and
1417 // also pause any further scheduling if there is really
1418 // nothing to do
1419 }
1420 }
1421 // It is possible that a refresh to another rank kicks things back into

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1513 }
1514 }
1515
1516 return make_pair(bank_mask, hidden_bank_prep);
1517}
1518
1519DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p)
1520 : EventManager(&_memory), memory(_memory),
1521 pwrStateTrans(PWR_IDLE), pwrState(PWR_IDLE), pwrStateTick(0),
1522 refreshState(REF_IDLE), refreshDueAt(0),
1523 power(_p, false), numBanksActive(0),
1524 activateEvent(*this), prechargeEvent(*this),
1525 refreshEvent(*this), powerEvent(*this)
1526{ }
1527
1528void
1529DRAMCtrl::Rank::startup(Tick ref_tick)
1530{
1531 assert(ref_tick > curTick());
1532
1533 pwrStateTick = curTick();

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1539
1540void
1541DRAMCtrl::Rank::suspend()
1542{
1543 deschedule(refreshEvent);
1544
1545 // Update the stats
1546 updatePowerStats();
1547}
1548
1549void
1550DRAMCtrl::Rank::checkDrainDone()
1551{
1552 // if this rank was waiting to drain it is now able to proceed to
1553 // precharge
1554 if (refreshState == REF_DRAIN) {
1555 DPRINTF(DRAM, "Refresh drain done, now precharging\n");
1556
1557 refreshState = REF_PRE;
1558
1559 // hand control back to the refresh event loop
1560 schedule(refreshEvent, curTick());
1561 }
1562}
1563
1564void
1565DRAMCtrl::Rank::flushCmdList()

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1597 // note that at this point numBanksActive could be back at
1598 // zero again due to a precharge scheduled in the future
1599 schedulePowerEvent(PWR_ACT, curTick());
1600}
1601
1602void
1603DRAMCtrl::Rank::processPrechargeEvent()
1604{
1605 // if we reached zero, then special conditions apply as we track
1606 // if all banks are precharged for the power models
1607 if (numBanksActive == 0) {
1608 // we should transition to the idle state when the last bank
1609 // is precharged
1610 schedulePowerEvent(PWR_IDLE, curTick());
1611 }
1612}
1613
1614void
1615DRAMCtrl::Rank::processRefreshEvent()
1616{
1617 // when first preparing the refresh, remember when it was due
1618 if (refreshState == REF_IDLE) {
1619 // remember when the refresh is due
1620 refreshDueAt = curTick();
1621
1622 // proceed to drain
1623 refreshState = REF_DRAIN;
1624
1625 DPRINTF(DRAM, "Refresh due\n");
1626 }
1627
1628 // let any scheduled read or write to the same rank go ahead,
1629 // after which it will
1630 // hand control back to this event loop
1631 if (refreshState == REF_DRAIN) {
1632 // if a request is at the moment being handled and this request is
1633 // accessing the current rank then wait for it to finish
1634 if ((rank == memory.activeRank)
1635 && (memory.nextReqEvent.scheduled())) {
1636 // hand control over to the request loop until it is
1637 // evaluated next
1638 DPRINTF(DRAM, "Refresh awaiting draining\n");
1639
1640 return;
1641 } else {
1642 refreshState = REF_PRE;
1643 }
1644 }
1645
1646 // at this point, ensure that all banks are precharged
1647 if (refreshState == REF_PRE) {
1648 // precharge any active bank if we are not already in the idle
1649 // state
1650 if (pwrState != PWR_IDLE) {
1651 // at the moment, we use a precharge all even if there is
1652 // only a single bank open
1653 DPRINTF(DRAM, "Precharging all\n");
1654
1655 // first determine when we can precharge
1656 Tick pre_at = curTick();
1657
1658 for (auto &b : banks) {

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1676 }
1677
1678 // precharge all banks in rank
1679 cmdList.push_back(Command(MemCommand::PREA, 0, pre_at));
1680
1681 DPRINTF(DRAMPower, "%llu,PREA,0,%d\n",
1682 divCeil(pre_at, memory.tCK) -
1683 memory.timeStampOffset, rank);
1684 } else {
1685 DPRINTF(DRAM, "All banks already precharged, starting refresh\n");
1686
1687 // go ahead and kick the power state machine into gear if
1688 // we are already idle
1689 schedulePowerEvent(PWR_REF, curTick());
1690 }
1691
1692 refreshState = REF_RUN;
1693 assert(numBanksActive == 0);
1694
1695 // wait for all banks to be precharged, at which point the
1696 // power state machine will transition to the idle state, and
1697 // automatically move to a refresh, at that point it will also
1698 // call this method to get the refresh event loop going again
1699 return;
1700 }
1701
1702 // last but not least we perform the actual refresh
1703 if (refreshState == REF_RUN) {
1704 // should never get here with any banks active
1705 assert(numBanksActive == 0);
1706 assert(pwrState == PWR_REF);
1707
1708 Tick ref_done_at = curTick() + memory.tRFC;
1709
1710 for (auto &b : banks) {
1711 b.actAllowedAt = ref_done_at;
1712 }
1713
1714 // at the moment this affects all ranks
1715 cmdList.push_back(Command(MemCommand::REF, 0, curTick()));
1716
1717 // Update the stats
1718 updatePowerStats();
1719
1720 DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) -
1721 memory.timeStampOffset, rank);
1722
1723 // make sure we did not wait so long that we cannot make up
1724 // for it
1725 if (refreshDueAt + memory.tREFI < ref_done_at) {
1726 fatal("Refresh was delayed so long we cannot catch up\n");
1727 }
1728
1729 // compensate for the delay in actually performing the refresh
1730 // when scheduling the next one
1731 schedule(refreshEvent, refreshDueAt + memory.tREFI - memory.tRP);
1732
1733 assert(!powerEvent.scheduled());
1734
1735 // move to the idle power state once the refresh is done, this
1736 // will also move the refresh state machine to the refresh
1737 // idle state
1738 schedulePowerEvent(PWR_IDLE, ref_done_at);
1739
1740 DPRINTF(DRAMState, "Refresh done at %llu and next refresh at %llu\n",
1741 ref_done_at, refreshDueAt + memory.tREFI);
1742 }
1743}
1744
1745void
1746DRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick)
1747{
1748 // respect causality
1749 assert(tick >= curTick());

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1759 } else {
1760 panic("Scheduled power event at %llu to state %d, "
1761 "with scheduled event at %llu to %d\n", tick, pwr_state,
1762 powerEvent.when(), pwrStateTrans);
1763 }
1764}
1765
1766void
1767DRAMCtrl::Rank::processPowerEvent()
1768{
1769 // remember where we were, and for how long
1770 Tick duration = curTick() - pwrStateTick;
1771 PowerState prev_state = pwrState;
1772
1773 // update the accounting
1774 pwrStateTime[prev_state] += duration;
1775
1776 pwrState = pwrStateTrans;
1777 pwrStateTick = curTick();
1778
1779 if (pwrState == PWR_IDLE) {
1780 DPRINTF(DRAMState, "All banks precharged\n");
1781
1782 // if we were refreshing, make sure we start scheduling requests again
1783 if (prev_state == PWR_REF) {
1784 DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration);
1785 assert(pwrState == PWR_IDLE);
1786
1787 // kick things into action again
1788 refreshState = REF_IDLE;
1789 // a request event could be already scheduled by the state
1790 // machine of the other rank
1791 if (!memory.nextReqEvent.scheduled())
1792 schedule(memory.nextReqEvent, curTick());
1793 } else {
1794 assert(prev_state == PWR_ACT);
1795
1796 // if we have a pending refresh, and are now moving to
1797 // the idle state, direclty transition to a refresh
1798 if (refreshState == REF_RUN) {
1799 // there should be nothing waiting at this point
1800 assert(!powerEvent.scheduled());
1801
1802 // update the state in zero time and proceed below
1803 pwrState = PWR_REF;
1804 }
1805 }
1806 }
1807
1808 // we transition to the refresh state, let the refresh state
1809 // machine know of this state update and let it deal with the
1810 // scheduling of the next power state transition as well as the
1811 // following refresh
1812 if (pwrState == PWR_REF) {
1813 DPRINTF(DRAMState, "Refreshing\n");
1814 // kick the refresh event loop into action again, and that
1815 // in turn will schedule a transition to the idle power
1816 // state once the refresh is done
1817 assert(refreshState == REF_RUN);
1818 processRefreshEvent();
1819 }
1820}
1821
1822void
1823DRAMCtrl::Rank::updatePowerStats()
1824{
1825 // All commands up to refresh have completed
1826 // flush cmdList to DRAMPower

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1847
1848 actEnergy = energy.act_energy * memory.devicesPerRank;
1849 preEnergy = energy.pre_energy * memory.devicesPerRank;
1850 readEnergy = energy.read_energy * memory.devicesPerRank;
1851 writeEnergy = energy.write_energy * memory.devicesPerRank;
1852 refreshEnergy = energy.ref_energy * memory.devicesPerRank;
1853 actBackEnergy = energy.act_stdby_energy * memory.devicesPerRank;
1854 preBackEnergy = energy.pre_stdby_energy * memory.devicesPerRank;
1855 totalEnergy = energy.total_energy * memory.devicesPerRank;
1856 averagePower = rank_power.average_power * memory.devicesPerRank;
1857}
1858
1859void
1860DRAMCtrl::Rank::computeStats()
1861{
1862 DPRINTF(DRAM,"Computing final stats\n");

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1875}
1876
1877void
1878DRAMCtrl::Rank::regStats()
1879{
1880 using namespace Stats;
1881
1882 pwrStateTime
1883 .init(5)
1884 .name(name() + ".memoryStateTime")
1885 .desc("Time in different power states");
1886 pwrStateTime.subname(0, "IDLE");
1887 pwrStateTime.subname(1, "REF");
1888 pwrStateTime.subname(2, "PRE_PDN");
1889 pwrStateTime.subname(3, "ACT");
1890 pwrStateTime.subname(4, "ACT_PDN");
1891
1892 actEnergy
1893 .name(name() + ".actEnergy")
1894 .desc("Energy for activate commands per rank (pJ)");
1895
1896 preEnergy
1897 .name(name() + ".preEnergy")
1898 .desc("Energy for precharge commands per rank (pJ)");

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1912 actBackEnergy
1913 .name(name() + ".actBackEnergy")
1914 .desc("Energy for active background per rank (pJ)");
1915
1916 preBackEnergy
1917 .name(name() + ".preBackEnergy")
1918 .desc("Energy for precharge background per rank (pJ)");
1919
1920 totalEnergy
1921 .name(name() + ".totalEnergy")
1922 .desc("Total energy per rank (pJ)");
1923
1924 averagePower
1925 .name(name() + ".averagePower")
1926 .desc("Core power per rank (mW)");
1927
1928 registerDumpCallback(new RankDumpCallback(this));
1929}
1930void
1931DRAMCtrl::regStats()
1932{
1933 using namespace Stats;
1934
1935 AbstractMemory::regStats();

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2210 // of that as well
2211 if (!(writeQueue.empty() && readQueue.empty() && respQueue.empty() &&
2212 allRanksDrained())) {
2213
2214 DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d,"
2215 " resp: %d\n", writeQueue.size(), readQueue.size(),
2216 respQueue.size());
2217
2218 // the only part that is not drained automatically over time
2219 // is the write queue, thus kick things into action if needed
2220 if (!writeQueue.empty() && !nextReqEvent.scheduled()) {
2221 schedule(nextReqEvent, curTick());
2222 }
2223 return DrainState::Draining;
2224 } else {
2225 return DrainState::Drained;
2226 }
2227}
2228
2229bool
2230DRAMCtrl::allRanksDrained() const

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