1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 */
44
45#include "base/bitfield.hh"
46#include "base/trace.hh"
47#include "debug/DRAM.hh"
48#include "debug/Drain.hh"
49#include "mem/dram_ctrl.hh"
50#include "sim/system.hh"
51
52using namespace std;
53
54DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
55 AbstractMemory(p),
56 port(name() + ".port", *this),
57 retryRdReq(false), retryWrReq(false),
58 rowHitFlag(false), busState(READ),
59 respondEvent(this), refreshEvent(this),
60 nextReqEvent(this), drainManager(NULL),
61 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
62 deviceRowBufferSize(p->device_rowbuffer_size),
63 devicesPerRank(p->devices_per_rank),
64 burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8),
65 rowBufferSize(devicesPerRank * deviceRowBufferSize),
66 columnsPerRowBuffer(rowBufferSize / burstSize),
67 ranksPerChannel(p->ranks_per_channel),
68 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),

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76 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
77 tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
78 tXAW(p->tXAW), activationLimit(p->activation_limit),
79 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
80 pageMgmt(p->page_policy),
81 maxAccessesPerRow(p->max_accesses_per_row),
82 frontendLatency(p->static_frontend_latency),
83 backendLatency(p->static_backend_latency),
84 busBusyUntil(0), refreshDueAt(0), refreshState(REF_IDLE), prevArrival(0),
85 nextReqTime(0), idleStartTick(0), numBanksActive(0)
86{
87 // create the bank states based on the dimensions of the ranks and
88 // banks
89 banks.resize(ranksPerChannel);
90 actTicks.resize(ranksPerChannel);
91 for (size_t c = 0; c < ranksPerChannel; ++c) {
92 banks[c].resize(banksPerRank);
93 actTicks[c].resize(activationLimit, 0);

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149 }
150}
151
152void
153DRAMCtrl::startup()
154{
155 // update the start tick for the precharge accounting to the
156 // current tick
157 idleStartTick = curTick();
158
159 // shift the bus busy time sufficiently far ahead that we never
160 // have to worry about negative values when computing the time for
161 // the next request, this will add an insignificant bubble at the
162 // start of simulation
163 busBusyUntil = curTick() + tRP + tRCD + tCL;
164
165 // print the configuration of the controller

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880DRAMCtrl::recordActivate(Tick act_tick, uint8_t rank, uint8_t bank,
881 uint16_t row)
882{
883 assert(0 <= rank && rank < ranksPerChannel);
884 assert(actTicks[rank].size() == activationLimit);
885
886 DPRINTF(DRAM, "Activate at tick %d\n", act_tick);
887
888 // idleStartTick is the tick when all the banks were
889 // precharged. Thus, the difference between act_tick and
890 // idleStartTick gives the time for which the DRAM is in an idle
891 // state with all banks precharged. Note that we may end up
892 // "changing history" by scheduling an activation before an
893 // already scheduled precharge, effectively canceling it out.
894 if (numBanksActive == 0 && act_tick > idleStartTick) {
895 prechargeAllTime += act_tick - idleStartTick;
896 }
897
898 // update the open row
899 assert(banks[rank][bank].openRow == Bank::NO_ROW);
900 banks[rank][bank].openRow = row;
901
902 // start counting anew, this covers both the case when we
903 // auto-precharged, and when this access is forced to
904 // precharge
905 banks[rank][bank].bytesAccessed = 0;

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911 DPRINTF(DRAM, "Activate bank at tick %lld, now got %d active\n",
912 act_tick, numBanksActive);
913
914 // start by enforcing tRRD
915 for(int i = 0; i < banksPerRank; i++) {
916 // next activate must not happen before tRRD
917 banks[rank][i].actAllowedAt = act_tick + tRRD;
918 }
919 // tRC should be added to activation tick of the bank currently accessed,
920 // where tRC = tRAS + tRP, this is just for a check as actAllowedAt for same
921 // bank is already captured by bank.freeAt and bank.tRASDoneAt
922 banks[rank][bank].actAllowedAt = act_tick + tRAS + tRP;
923
924 // next, we deal with tXAW, if the activation limit is disabled
925 // then we are done
926 if (actTicks[rank].empty())

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946 // oldest in our window of X
947 if (actTicks[rank].back() && (act_tick - actTicks[rank].back()) < tXAW) {
948 DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate no earlier "
949 "than %d\n", activationLimit, actTicks[rank].back() + tXAW);
950 for(int j = 0; j < banksPerRank; j++)
951 // next activate must not happen before end of window
952 banks[rank][j].actAllowedAt = actTicks[rank].back() + tXAW;
953 }
954}
955
956void
957DRAMCtrl::prechargeBank(Bank& bank, Tick free_at)
958{
959 // make sure the bank has an open row
960 assert(bank.openRow != Bank::NO_ROW);
961
962 // sample the bytes per activate here since we are closing
963 // the page
964 bytesPerActivate.sample(bank.bytesAccessed);
965
966 bank.openRow = Bank::NO_ROW;
967
968 bank.freeAt = free_at;
969
970 assert(numBanksActive != 0);
971 --numBanksActive;
972
973 DPRINTF(DRAM, "Precharged bank, done at tick %lld, now got %d active\n",
974 bank.freeAt, numBanksActive);
975
976 // if we reached zero, then special conditions apply as we track
977 // if all banks are precharged for the power models
978 if (numBanksActive == 0) {
979 idleStartTick = std::max(idleStartTick, bank.freeAt);
980 DPRINTF(DRAM, "All banks precharged at tick: %ld\n",
981 idleStartTick);
982 }
983}
984
985void
986DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
987{
988
989 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",

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1407 return;
1408 } else {
1409 refreshState = REF_PRE;
1410 }
1411 }
1412
1413 // at this point, ensure that all banks are precharged
1414 if (refreshState == REF_PRE) {
1415 DPRINTF(DRAM, "Precharging all\n");
1416
1417 // precharge any active bank
1418 for (int i = 0; i < ranksPerChannel; i++) {
1419 for (int j = 0; j < banksPerRank; j++) {
1420 if (banks[i][j].openRow != Bank::NO_ROW) {
1421 // respect both causality and any existing bank
1422 // constraints
1423 Tick free_at = std::max(std::max(banks[i][j].freeAt,
1424 banks[i][j].tRASDoneAt),
1425 curTick()) + tRP;
1426
1427 prechargeBank(banks[i][j], free_at);
1428 }
1429 }
1430 }
1431
1432 if (numBanksActive != 0)
1433 panic("Refresh scheduled with %d active banks\n", numBanksActive);
1434
1435 // advance the state
1436 refreshState = REF_RUN;
1437
1438 // call ourselves in the future
1439 schedule(refreshEvent, std::max(curTick(), idleStartTick));
1440 return;
1441 }
1442
1443 // last but not least we perform the actual refresh
1444 if (refreshState == REF_RUN) {
1445 // should never get here with any banks active
1446 assert(numBanksActive == 0);
1447
1448 Tick banksFree = curTick() + tRFC;
1449
1450 for (int i = 0; i < ranksPerChannel; i++) {
1451 for (int j = 0; j < banksPerRank; j++) {
1452 banks[i][j].freeAt = banksFree;
1453 }
1454 }
1455
1456 // make sure we did not wait so long that we cannot make up
1457 // for it
1458 if (refreshDueAt + tREFI < banksFree) {
1459 fatal("Refresh was delayed so long we cannot catch up\n");
1460 }
1461
1462 // compensate for the delay in actually performing the refresh
1463 // when scheduling the next one
1464 schedule(refreshEvent, refreshDueAt + tREFI - tRP);
1465
1466 // back to business as usual
1467 refreshState = REF_IDLE;
1468
1469 // we are now refreshing until tRFC is done
1470 idleStartTick = banksFree;
1471
1472 // kick the normal request processing loop into action again
1473 // as early as possible, i.e. when the request is done, the
1474 // scheduling of this event also prevents any new requests
1475 // from going ahead before the scheduled point in time
1476 nextReqTime = banksFree;
1477 schedule(nextReqEvent, nextReqTime);
1478 }
1479}
1480
1481void
1482DRAMCtrl::regStats()
1483{
1484 using namespace Stats;
1485
1486 AbstractMemory::regStats();
1487
1488 readReqs
1489 .name(name() + ".readReqs")

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1739 pageHitRate
1740 .name(name() + ".pageHitRate")
1741 .desc("Row buffer hit rate, read and write combined")
1742 .precision(2);
1743
1744 pageHitRate = (writeRowHits + readRowHits) /
1745 (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100;
1746
1747 prechargeAllPercent
1748 .name(name() + ".prechargeAllPercent")
1749 .desc("Percentage of time for which DRAM has all the banks in "
1750 "precharge state")
1751 .precision(2);
1752
1753 prechargeAllPercent = prechargeAllTime / simTicks * 100;
1754}
1755
1756void
1757DRAMCtrl::recvFunctional(PacketPtr pkt)
1758{
1759 // rely on the abstract memory
1760 functionalAccess(pkt);
1761}

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