1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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65 rowBufferSize(devicesPerRank * deviceRowBufferSize),
66 columnsPerRowBuffer(rowBufferSize / burstSize),
67 ranksPerChannel(p->ranks_per_channel),
68 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
69 readBufferSize(p->read_buffer_size),
70 writeBufferSize(p->write_buffer_size),
71 writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
72 writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
73 minWritesPerSwitch(p->min_writes_per_switch), writesThisTime(0),
74 tWTR(p->tWTR), tBURST(p->tBURST),
75 tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
76 tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
77 tXAW(p->tXAW), activationLimit(p->activation_limit),
78 memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
79 pageMgmt(p->page_policy),
80 maxAccessesPerRow(p->max_accesses_per_row),
81 frontendLatency(p->static_frontend_latency),

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394 DRAMPacket* dram_pkt = writeQueue.front();
395 // sanity check
396 assert(dram_pkt->size <= burstSize);
397 doDRAMAccess(dram_pkt);
398
399 writeQueue.pop_front();
400 delete dram_pkt;
401
402 ++writesThisTime;
403
404 DPRINTF(DRAM, "Writing, bus busy for %lld ticks, banks busy "
405 "for %lld ticks\n", busBusyUntil - temp1, maxBankFreeAt() - temp2);
406
407 // If we emptied the write queue, or got below the threshold and
408 // are not draining, or we have reads waiting and have done enough
409 // writes, then switch to reads. The retry above could already
410 // have caused it to be scheduled, so first check
411 if (writeQueue.empty() ||
412 (writeQueue.size() < writeLowThreshold && !drainManager) ||
413 (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) {
414 // turn the bus back around for reads again
415 busBusyUntil += tWTR;
416 stopReads = false;
417 writesThisTime = 0;
418
419 if (!nextReqEvent.scheduled())
420 schedule(nextReqEvent, busBusyUntil);
421 } else {
422 assert(!writeEvent.scheduled());
423 DPRINTF(DRAM, "Next write scheduled at %lld\n", newTime);
424 schedule(writeEvent, newTime);

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436 drainManager = NULL;
437 }
438}
439
440
441void
442DRAMCtrl::triggerWrites()
443{
444 DPRINTF(DRAM, "Writes triggered at %lld\n", curTick());
445 // Flag variable to stop any more read scheduling
446 stopReads = true;
447
448 Tick write_start_time = std::max(busBusyUntil, curTick()) + tWTR;
449
450 DPRINTF(DRAM, "Writes scheduled at %lld\n", write_start_time);
451
452 assert(write_start_time >= curTick());
453 assert(!writeEvent.scheduled());
454 schedule(writeEvent, write_start_time);
455}
456
457void
458DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
459{

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1193 dram_pkt->readyTime - dram_pkt->entryTime);
1194
1195 // Update the minimum timing between the requests
1196 newTime = (busBusyUntil > tRP + tRCD + tCL) ?
1197 std::max(busBusyUntil - (tRP + tRCD + tCL), curTick()) : curTick();
1198
1199 // Update the access related stats
1200 if (dram_pkt->isRead) {
1201 if (rowHitFlag)
1202 readRowHits++;
1203 bytesReadDRAM += burstSize;
1204 perBankRdBursts[dram_pkt->bankId]++;
1205 } else {
1206 if (rowHitFlag)
1207 writeRowHits++;
1208 bytesWritten += burstSize;
1209 perBankWrBursts[dram_pkt->bankId]++;
1210
1211 // At this point, commonality between reads and writes ends.
1212 // For writes, we are done since we long ago responded to the
1213 // requestor.

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1513 .desc("What write queue length does an incoming req see");
1514
1515 bytesPerActivate
1516 .init(maxAccessesPerRow)
1517 .name(name() + ".bytesPerActivate")
1518 .desc("Bytes accessed per row activation")
1519 .flags(nozero);
1520
1521 bytesReadDRAM
1522 .name(name() + ".bytesReadDRAM")
1523 .desc("Total number of bytes read from DRAM");
1524
1525 bytesReadWrQ
1526 .name(name() + ".bytesReadWrQ")
1527 .desc("Total number of bytes read from write queue");
1528

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