1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1037 if (row_hit)
1038 writeRowHits++;
1039 bytesWritten += burstSize;
1040 perBankWrBursts[dram_pkt->bankId]++;
1041 }
1042}
1043
1044void
1045DRAMCtrl::processNextReqEvent()
1046{
1047 if (busState == READ_TO_WRITE) {
1048 DPRINTF(DRAM, "Switching to writes after %d reads with %d reads "
1049 "waiting\n", readsThisTime, readQueue.size());
1050
1051 // sample and reset the read-related stats as we are now
1052 // transitioning to writes, and all reads are done

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1106 // event for the next request
1107 return;
1108 }
1109 } else {
1110 // Figure out which read request goes next, and move it to the
1111 // front of the read queue
1112 chooseNext(readQueue);
1113
1114 DRAMPacket* dram_pkt = readQueue.front();
1115
1116 doDRAMAccess(dram_pkt);
1117
1118 // At this point we're done dealing with the request
1119 readQueue.pop_front();
1120
1121 // sanity check
1122 assert(dram_pkt->size <= burstSize);
1123 assert(dram_pkt->readyTime >= curTick());
1124
1125 // Insert into response queue. It will be sent back to the
1126 // requestor at its readyTime
1127 if (respQueue.empty()) {
1128 assert(!respondEvent.scheduled());
1129 schedule(respondEvent, dram_pkt->readyTime);
1130 } else {
1131 assert(respQueue.back()->readyTime <= dram_pkt->readyTime);
1132 assert(respondEvent.scheduled());
1133 }
1134
1135 respQueue.push_back(dram_pkt);
1136
1137 // we have so many writes that we have to transition
1138 if (writeQueue.size() > writeHighThreshold) {
1139 switch_to_writes = true;
1140 }
1141 }
1142
1143 // switching to writes, either because the read queue is empty
1144 // and the writes have passed the low threshold (or we are

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