comm_monitor.hh (11173:3a4d1b5cd05c) | comm_monitor.hh (11804:220375a47eeb) |
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1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited | 1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited |
3 * All rights reserved | 3 * Copyright (c) 2016 Google Inc. 4 * All rights reserved. |
4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, --- 19 unchanged lines hidden (view full) --- 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson | 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, --- 19 unchanged lines hidden (view full) --- 32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Authors: Thomas Grass 39 * Andreas Hansson |
40 * Rahul Thakur |
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39 */ 40 41#ifndef __MEM_COMM_MONITOR_HH__ 42#define __MEM_COMM_MONITOR_HH__ 43 44#include "base/statistics.hh" 45#include "mem/mem_object.hh" 46#include "params/CommMonitor.hh" --- 305 unchanged lines hidden (view full) --- 352 353 /** Histogram of number of timing write transactions per time bin */ 354 Stats::Histogram writeTransHist; 355 unsigned int writeTrans; 356 357 /** Disable flag for address distributions. */ 358 bool disableAddrDists; 359 | 41 */ 42 43#ifndef __MEM_COMM_MONITOR_HH__ 44#define __MEM_COMM_MONITOR_HH__ 45 46#include "base/statistics.hh" 47#include "mem/mem_object.hh" 48#include "params/CommMonitor.hh" --- 305 unchanged lines hidden (view full) --- 354 355 /** Histogram of number of timing write transactions per time bin */ 356 Stats::Histogram writeTransHist; 357 unsigned int writeTrans; 358 359 /** Disable flag for address distributions. */ 360 bool disableAddrDists; 361 |
362 /** Address mask for sources of read accesses to be captured */ 363 const Addr readAddrMask; 364 365 /** Address mask for sources of write accesses to be captured */ 366 const Addr writeAddrMask; 367 |
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360 /** 361 * Histogram of number of read accesses to addresses over 362 * time. 363 */ 364 Stats::SparseHistogram readAddrDist; 365 366 /** 367 * Histogram of number of write accesses to addresses over --- 12 unchanged lines hidden (view full) --- 380 readBytes(0), writtenBytes(0), 381 disableLatencyHists(params->disable_latency_hists), 382 disableITTDists(params->disable_itt_dists), 383 timeOfLastRead(0), timeOfLastWrite(0), timeOfLastReq(0), 384 disableOutstandingHists(params->disable_outstanding_hists), 385 outstandingReadReqs(0), outstandingWriteReqs(0), 386 disableTransactionHists(params->disable_transaction_hists), 387 readTrans(0), writeTrans(0), | 368 /** 369 * Histogram of number of read accesses to addresses over 370 * time. 371 */ 372 Stats::SparseHistogram readAddrDist; 373 374 /** 375 * Histogram of number of write accesses to addresses over --- 12 unchanged lines hidden (view full) --- 388 readBytes(0), writtenBytes(0), 389 disableLatencyHists(params->disable_latency_hists), 390 disableITTDists(params->disable_itt_dists), 391 timeOfLastRead(0), timeOfLastWrite(0), timeOfLastReq(0), 392 disableOutstandingHists(params->disable_outstanding_hists), 393 outstandingReadReqs(0), outstandingWriteReqs(0), 394 disableTransactionHists(params->disable_transaction_hists), 395 readTrans(0), writeTrans(0), |
388 disableAddrDists(params->disable_addr_dists) | 396 disableAddrDists(params->disable_addr_dists), 397 readAddrMask(params->read_addr_mask), 398 writeAddrMask(params->write_addr_mask) |
389 { } 390 | 399 { } 400 |
401 void updateReqStats(const ProbePoints::PacketInfo& pkt, bool is_atomic, 402 bool expects_response); 403 void updateRespStats(const ProbePoints::PacketInfo& pkt, Tick latency, 404 bool is_atomic); |
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391 }; 392 393 /** This function is called periodically at the end of each time bin */ 394 void samplePeriodic(); 395 396 /** Periodic event called at the end of each simulation time bin */ 397 EventWrapper<CommMonitor, &CommMonitor::samplePeriodic> samplePeriodicEvent; 398 399 /** 400 *@{ 401 * @name Configuration 402 */ 403 404 /** Length of simulation time bin*/ 405 const Tick samplePeriodTicks; 406 /** Sample period in seconds */ 407 const double samplePeriod; 408 | 405 }; 406 407 /** This function is called periodically at the end of each time bin */ 408 void samplePeriodic(); 409 410 /** Periodic event called at the end of each simulation time bin */ 411 EventWrapper<CommMonitor, &CommMonitor::samplePeriodic> samplePeriodicEvent; 412 413 /** 414 *@{ 415 * @name Configuration 416 */ 417 418 /** Length of simulation time bin*/ 419 const Tick samplePeriodTicks; 420 /** Sample period in seconds */ 421 const double samplePeriod; 422 |
409 /** Address mask for sources of read accesses to be captured */ 410 const Addr readAddrMask; 411 412 /** Address mask for sources of write accesses to be captured */ 413 const Addr writeAddrMask; 414 | |
415 /** @} */ 416 417 /** Instantiate stats */ 418 MonitorStats stats; 419 420 protected: // Probe points 421 /** 422 * @{ --- 13 unchanged lines hidden --- | 423 /** @} */ 424 425 /** Instantiate stats */ 426 MonitorStats stats; 427 428 protected: // Probe points 429 /** 430 * @{ --- 13 unchanged lines hidden --- |