1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 * Andreas Hansson
39 */
40
41#ifndef __MEM_COMM_MONITOR_HH__
42#define __MEM_COMM_MONITOR_HH__
43
44#include "base/statistics.hh"
45#include "mem/mem_object.hh"
46#include "mem/stack_dist_calc.hh"
46#include "params/CommMonitor.hh"
47#include "proto/protoio.hh"
48#include "sim/probe/mem.hh"
49#include "sim/system.hh"
50
51/**
52 * The communication monitor is a MemObject which can monitor statistics of
53 * the communication happening between two ports in the memory system.
54 *
55 * Currently the following stats are implemented: Histograms of read/write
56 * transactions, read/write burst lengths, read/write bandwidth,
57 * outstanding read/write requests, read latency and inter transaction time
58 * (read-read, write-write, read/write-read/write). Furthermore it allows
59 * to capture the number of accesses to an address over time ("heat map").
60 * All stats can be disabled from Python.
61 */
62class CommMonitor : public MemObject
63{
64
65 public: // Construction & SimObject interfaces
66
67 /** Parameters of communication monitor */
68 typedef CommMonitorParams Params;
69 const Params* params() const
70 { return reinterpret_cast<const Params*>(_params); }
71
72 /**
73 * Constructor based on the Python params
74 *
75 * @param params Python parameters
76 */
77 CommMonitor(Params* params);
78
79 /** Destructor */
80 ~CommMonitor();
81
82 void init() M5_ATTR_OVERRIDE;
83 void regStats() M5_ATTR_OVERRIDE;
84 void startup() M5_ATTR_OVERRIDE;
85 void regProbePoints() M5_ATTR_OVERRIDE;
86
87 public: // MemObject interfaces
88 BaseMasterPort& getMasterPort(const std::string& if_name,
89 PortID idx = InvalidPortID) M5_ATTR_OVERRIDE;
90
91 BaseSlavePort& getSlavePort(const std::string& if_name,
92 PortID idx = InvalidPortID) M5_ATTR_OVERRIDE;
93
94 private:
95
96 /**
97 * Sender state class for the monitor so that we can annotate
98 * packets with a transmit time and receive time.
99 */
100 class CommMonitorSenderState : public Packet::SenderState
101 {
102
103 public:
104
105 /**
106 * Construct a new sender state and store the time so we can
107 * calculate round-trip latency.
108 *
109 * @param _transmitTime Time of packet transmission
110 */
111 CommMonitorSenderState(Tick _transmitTime)
112 : transmitTime(_transmitTime)
113 { }
114
115 /** Destructor */
116 ~CommMonitorSenderState() { }
117
118 /** Tick when request is transmitted */
119 Tick transmitTime;
120
121 };
122
123 /**
124 * This is the master port of the communication monitor. All recv
125 * functions call a function in CommMonitor, where the
126 * send function of the slave port is called. Besides this, these
127 * functions can also perform actions for capturing statistics.
128 */
129 class MonitorMasterPort : public MasterPort
130 {
131
132 public:
133
134 MonitorMasterPort(const std::string& _name, CommMonitor& _mon)
135 : MasterPort(_name, &_mon), mon(_mon)
136 { }
137
138 protected:
139
140 void recvFunctionalSnoop(PacketPtr pkt)
141 {
142 mon.recvFunctionalSnoop(pkt);
143 }
144
145 Tick recvAtomicSnoop(PacketPtr pkt)
146 {
147 return mon.recvAtomicSnoop(pkt);
148 }
149
150 bool recvTimingResp(PacketPtr pkt)
151 {
152 return mon.recvTimingResp(pkt);
153 }
154
155 void recvTimingSnoopReq(PacketPtr pkt)
156 {
157 mon.recvTimingSnoopReq(pkt);
158 }
159
160 void recvRangeChange()
161 {
162 mon.recvRangeChange();
163 }
164
165 bool isSnooping() const
166 {
167 return mon.isSnooping();
168 }
169
170 void recvReqRetry()
171 {
172 mon.recvReqRetry();
173 }
174
175 private:
176
177 CommMonitor& mon;
178
179 };
180
181 /** Instance of master port, facing the memory side */
182 MonitorMasterPort masterPort;
183
184 /**
185 * This is the slave port of the communication monitor. All recv
186 * functions call a function in CommMonitor, where the
187 * send function of the master port is called. Besides this, these
188 * functions can also perform actions for capturing statistics.
189 */
190 class MonitorSlavePort : public SlavePort
191 {
192
193 public:
194
195 MonitorSlavePort(const std::string& _name, CommMonitor& _mon)
196 : SlavePort(_name, &_mon), mon(_mon)
197 { }
198
199 protected:
200
201 void recvFunctional(PacketPtr pkt)
202 {
203 mon.recvFunctional(pkt);
204 }
205
206 Tick recvAtomic(PacketPtr pkt)
207 {
208 return mon.recvAtomic(pkt);
209 }
210
211 bool recvTimingReq(PacketPtr pkt)
212 {
213 return mon.recvTimingReq(pkt);
214 }
215
216 bool recvTimingSnoopResp(PacketPtr pkt)
217 {
218 return mon.recvTimingSnoopResp(pkt);
219 }
220
221 AddrRangeList getAddrRanges() const
222 {
223 return mon.getAddrRanges();
224 }
225
226 void recvRespRetry()
227 {
228 mon.recvRespRetry();
229 }
230
231 private:
232
233 CommMonitor& mon;
234
235 };
236
237 /** Instance of slave port, i.e. on the CPU side */
238 MonitorSlavePort slavePort;
239
240 void recvFunctional(PacketPtr pkt);
241
242 void recvFunctionalSnoop(PacketPtr pkt);
243
244 Tick recvAtomic(PacketPtr pkt);
245
246 Tick recvAtomicSnoop(PacketPtr pkt);
247
248 bool recvTimingReq(PacketPtr pkt);
249
250 bool recvTimingResp(PacketPtr pkt);
251
252 void recvTimingSnoopReq(PacketPtr pkt);
253
254 bool recvTimingSnoopResp(PacketPtr pkt);
255
256 AddrRangeList getAddrRanges() const;
257
258 bool isSnooping() const;
259
260 void recvReqRetry();
261
262 void recvRespRetry();
263
264 void recvRangeChange();
265
266 /** Stats declarations, all in a struct for convenience. */
267 struct MonitorStats
268 {
269
270 /** Disable flag for burst length historgrams **/
271 bool disableBurstLengthHists;
272
273 /** Histogram of read burst lengths */
274 Stats::Histogram readBurstLengthHist;
275
276 /** Histogram of write burst lengths */
277 Stats::Histogram writeBurstLengthHist;
278
279 /** Disable flag for the bandwidth histograms */
280 bool disableBandwidthHists;
281
282 /**
283 * Histogram for read bandwidth per sample window. The
284 * internal counter is an unsigned int rather than a stat.
285 */
286 unsigned int readBytes;
287 Stats::Histogram readBandwidthHist;
288 Stats::Formula averageReadBW;
289 Stats::Scalar totalReadBytes;
290
291 /**
292 * Histogram for write bandwidth per sample window. The
293 * internal counter is an unsigned int rather than a stat.
294 */
295 unsigned int writtenBytes;
296 Stats::Histogram writeBandwidthHist;
297 Stats::Formula averageWriteBW;
298 Stats::Scalar totalWrittenBytes;
299
300 /** Disable flag for latency histograms. */
301 bool disableLatencyHists;
302
303 /** Histogram of read request-to-response latencies */
304 Stats::Histogram readLatencyHist;
305
306 /** Histogram of write request-to-response latencies */
307 Stats::Histogram writeLatencyHist;
308
309 /** Disable flag for ITT distributions. */
310 bool disableITTDists;
311
312 /**
313 * Inter transaction time (ITT) distributions. There are
314 * histograms of the time between two read, write or arbitrary
315 * accesses. The time of a request is the tick at which the
316 * request is forwarded by the monitor.
317 */
318 Stats::Distribution ittReadRead;
319 Stats::Distribution ittWriteWrite;
320 Stats::Distribution ittReqReq;
321 Tick timeOfLastRead;
322 Tick timeOfLastWrite;
323 Tick timeOfLastReq;
324
325 /** Disable flag for outstanding histograms. */
326 bool disableOutstandingHists;
327
328 /**
329 * Histogram of outstanding read requests. Counter for
330 * outstanding read requests is an unsigned integer because
331 * it should not be reset when stats are reset.
332 */
333 Stats::Histogram outstandingReadsHist;
334 unsigned int outstandingReadReqs;
335
336 /**
337 * Histogram of outstanding write requests. Counter for
338 * outstanding write requests is an unsigned integer because
339 * it should not be reset when stats are reset.
340 */
341 Stats::Histogram outstandingWritesHist;
342 unsigned int outstandingWriteReqs;
343
344 /** Disable flag for transaction histograms. */
345 bool disableTransactionHists;
346
347 /** Histogram of number of read transactions per time bin */
348 Stats::Histogram readTransHist;
349 unsigned int readTrans;
350
351 /** Histogram of number of timing write transactions per time bin */
352 Stats::Histogram writeTransHist;
353 unsigned int writeTrans;
354
355 /** Disable flag for address distributions. */
356 bool disableAddrDists;
357
358 /**
359 * Histogram of number of read accesses to addresses over
360 * time.
361 */
362 Stats::SparseHistogram readAddrDist;
363
364 /**
365 * Histogram of number of write accesses to addresses over
366 * time.
367 */
368 Stats::SparseHistogram writeAddrDist;
369
370 /**
371 * Create the monitor stats and initialise all the members
372 * that are not statistics themselves, but used to control the
373 * stats or track values during a sample period.
374 */
375 MonitorStats(const CommMonitorParams* params) :
376 disableBurstLengthHists(params->disable_burst_length_hists),
377 disableBandwidthHists(params->disable_bandwidth_hists),
378 readBytes(0), writtenBytes(0),
379 disableLatencyHists(params->disable_latency_hists),
380 disableITTDists(params->disable_itt_dists),
381 timeOfLastRead(0), timeOfLastWrite(0), timeOfLastReq(0),
382 disableOutstandingHists(params->disable_outstanding_hists),
383 outstandingReadReqs(0), outstandingWriteReqs(0),
384 disableTransactionHists(params->disable_transaction_hists),
385 readTrans(0), writeTrans(0),
386 disableAddrDists(params->disable_addr_dists)
387 { }
388
389 };
390
391 /** This function is called periodically at the end of each time bin */
392 void samplePeriodic();
393
394 /**
395 * Callback to flush and close all open output streams on exit. If
396 * we were calling the destructor it could be done there.
397 */
398 void closeStreams();
399
400 /** Periodic event called at the end of each simulation time bin */
401 EventWrapper<CommMonitor, &CommMonitor::samplePeriodic> samplePeriodicEvent;
402
403 /**
404 *@{
405 * @name Configuration
406 */
407
408 /** Length of simulation time bin*/
409 const Tick samplePeriodTicks;
410 /** Sample period in seconds */
411 const double samplePeriod;
412
413 /** Address mask for sources of read accesses to be captured */
414 const Addr readAddrMask;
415
416 /** Address mask for sources of write accesses to be captured */
417 const Addr writeAddrMask;
418
420 /** Optional stack distance calculator */
421 StackDistCalc *const stackDistCalc;
422
419 /** The system in which the monitor lives */
420 System *const system;
421
422 /** @} */
423
424 /** Output stream for a potential trace. */
425 ProtoOutputStream *traceStream;
426
427 /** Instantiate stats */
428 MonitorStats stats;
429
430 protected: // Probe points
431 /**
432 * @{
433 * @name Memory system probe points
434 */
435
436 /** Successfully forwarded request packet */
437 ProbePoints::PacketUPtr ppPktReq;
438
439 /** Successfully forwarded response packet */
440 ProbePoints::PacketUPtr ppPktResp;
441
442 /** @} */
443};
444
445#endif //__MEM_COMM_MONITOR_HH__