1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited |
3 * Copyright (c) 2016 Google Inc. 4 * All rights reserved. |
5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, --- 19 unchanged lines hidden (view full) --- 32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Authors: Thomas Grass 39 * Andreas Hansson |
40 * Rahul Thakur |
41 */ 42 43#ifndef __MEM_COMM_MONITOR_HH__ 44#define __MEM_COMM_MONITOR_HH__ 45 46#include "base/statistics.hh" 47#include "mem/mem_object.hh" 48#include "params/CommMonitor.hh" --- 305 unchanged lines hidden (view full) --- 354 355 /** Histogram of number of timing write transactions per time bin */ 356 Stats::Histogram writeTransHist; 357 unsigned int writeTrans; 358 359 /** Disable flag for address distributions. */ 360 bool disableAddrDists; 361 |
362 /** Address mask for sources of read accesses to be captured */ 363 const Addr readAddrMask; 364 365 /** Address mask for sources of write accesses to be captured */ 366 const Addr writeAddrMask; 367 |
368 /** 369 * Histogram of number of read accesses to addresses over 370 * time. 371 */ 372 Stats::SparseHistogram readAddrDist; 373 374 /** 375 * Histogram of number of write accesses to addresses over --- 12 unchanged lines hidden (view full) --- 388 readBytes(0), writtenBytes(0), 389 disableLatencyHists(params->disable_latency_hists), 390 disableITTDists(params->disable_itt_dists), 391 timeOfLastRead(0), timeOfLastWrite(0), timeOfLastReq(0), 392 disableOutstandingHists(params->disable_outstanding_hists), 393 outstandingReadReqs(0), outstandingWriteReqs(0), 394 disableTransactionHists(params->disable_transaction_hists), 395 readTrans(0), writeTrans(0), |
396 disableAddrDists(params->disable_addr_dists), 397 readAddrMask(params->read_addr_mask), 398 writeAddrMask(params->write_addr_mask) |
399 { } 400 |
401 void updateReqStats(const ProbePoints::PacketInfo& pkt, bool is_atomic, 402 bool expects_response); 403 void updateRespStats(const ProbePoints::PacketInfo& pkt, Tick latency, 404 bool is_atomic); |
405 }; 406 407 /** This function is called periodically at the end of each time bin */ 408 void samplePeriodic(); 409 410 /** Periodic event called at the end of each simulation time bin */ 411 EventWrapper<CommMonitor, &CommMonitor::samplePeriodic> samplePeriodicEvent; 412 413 /** 414 *@{ 415 * @name Configuration 416 */ 417 418 /** Length of simulation time bin*/ 419 const Tick samplePeriodTicks; 420 /** Sample period in seconds */ 421 const double samplePeriod; 422 |
423 /** @} */ 424 425 /** Instantiate stats */ 426 MonitorStats stats; 427 428 protected: // Probe points 429 /** 430 * @{ --- 13 unchanged lines hidden --- |