1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 * Andreas Hansson
39 */
40
41#ifndef __MEM_COMM_MONITOR_HH__
42#define __MEM_COMM_MONITOR_HH__
43
44#include "base/statistics.hh"
45#include "mem/mem_object.hh"
46#include "mem/stack_dist_calc.hh"
47#include "params/CommMonitor.hh"
48#include "proto/protoio.hh"
49#include "sim/probe/mem.hh"
50#include "sim/system.hh"
51
52/**
53 * The communication monitor is a MemObject which can monitor statistics of
54 * the communication happening between two ports in the memory system.
55 *
56 * Currently the following stats are implemented: Histograms of read/write
57 * transactions, read/write burst lengths, read/write bandwidth,
58 * outstanding read/write requests, read latency and inter transaction time
59 * (read-read, write-write, read/write-read/write). Furthermore it allows
60 * to capture the number of accesses to an address over time ("heat map").
61 * All stats can be disabled from Python.
62 */
63class CommMonitor : public MemObject
64{
65
66 public: // Construction & SimObject interfaces
67
68 /** Parameters of communication monitor */
69 typedef CommMonitorParams Params;
70 const Params* params() const
71 { return reinterpret_cast<const Params*>(_params); }
72
73 /**
74 * Constructor based on the Python params
75 *
76 * @param params Python parameters
77 */
78 CommMonitor(Params* params);
79
80 /** Destructor */
81 ~CommMonitor();
82
83 void init() M5_ATTR_OVERRIDE;
84 void regStats() M5_ATTR_OVERRIDE;
85 void startup() M5_ATTR_OVERRIDE;
86 void regProbePoints() M5_ATTR_OVERRIDE;
87
88 public: // MemObject interfaces
89 BaseMasterPort& getMasterPort(const std::string& if_name,
90 PortID idx = InvalidPortID) M5_ATTR_OVERRIDE;
91
92 BaseSlavePort& getSlavePort(const std::string& if_name,
93 PortID idx = InvalidPortID) M5_ATTR_OVERRIDE;
94
95 private:
96
97 /**
98 * Sender state class for the monitor so that we can annotate
99 * packets with a transmit time and receive time.
100 */
101 class CommMonitorSenderState : public Packet::SenderState
102 {
103
104 public:
105
106 /**
107 * Construct a new sender state and store the time so we can
108 * calculate round-trip latency.
109 *
110 * @param _transmitTime Time of packet transmission
111 */
112 CommMonitorSenderState(Tick _transmitTime)
113 : transmitTime(_transmitTime)
114 { }
115
116 /** Destructor */
117 ~CommMonitorSenderState() { }
118
119 /** Tick when request is transmitted */
120 Tick transmitTime;
121
122 };
123
124 /**
125 * This is the master port of the communication monitor. All recv
126 * functions call a function in CommMonitor, where the
127 * send function of the slave port is called. Besides this, these
128 * functions can also perform actions for capturing statistics.
129 */
130 class MonitorMasterPort : public MasterPort
131 {
132
133 public:
134
135 MonitorMasterPort(const std::string& _name, CommMonitor& _mon)
136 : MasterPort(_name, &_mon), mon(_mon)
137 { }
138
139 protected:
140
141 void recvFunctionalSnoop(PacketPtr pkt)
142 {
143 mon.recvFunctionalSnoop(pkt);
144 }
145
146 Tick recvAtomicSnoop(PacketPtr pkt)
147 {
148 return mon.recvAtomicSnoop(pkt);
149 }
150
151 bool recvTimingResp(PacketPtr pkt)
152 {
153 return mon.recvTimingResp(pkt);
154 }
155
156 void recvTimingSnoopReq(PacketPtr pkt)
157 {
158 mon.recvTimingSnoopReq(pkt);
159 }
160
161 void recvRangeChange()
162 {
163 mon.recvRangeChange();
164 }
165
166 bool isSnooping() const
167 {
168 return mon.isSnooping();
169 }
170
171 void recvReqRetry()
172 {
173 mon.recvReqRetry();
174 }
175
176 private:
177
178 CommMonitor& mon;
179
180 };
181
182 /** Instance of master port, facing the memory side */
183 MonitorMasterPort masterPort;
184
185 /**
186 * This is the slave port of the communication monitor. All recv
187 * functions call a function in CommMonitor, where the
188 * send function of the master port is called. Besides this, these
189 * functions can also perform actions for capturing statistics.
190 */
191 class MonitorSlavePort : public SlavePort
192 {
193
194 public:
195
196 MonitorSlavePort(const std::string& _name, CommMonitor& _mon)
197 : SlavePort(_name, &_mon), mon(_mon)
198 { }
199
200 protected:
201
202 void recvFunctional(PacketPtr pkt)
203 {
204 mon.recvFunctional(pkt);
205 }
206
207 Tick recvAtomic(PacketPtr pkt)
208 {
209 return mon.recvAtomic(pkt);
210 }
211
212 bool recvTimingReq(PacketPtr pkt)
213 {
214 return mon.recvTimingReq(pkt);
215 }
216
217 bool recvTimingSnoopResp(PacketPtr pkt)
218 {
219 return mon.recvTimingSnoopResp(pkt);
220 }
221
222 AddrRangeList getAddrRanges() const
223 {
224 return mon.getAddrRanges();
225 }
226
227 void recvRespRetry()
228 {
229 mon.recvRespRetry();
230 }
231
232 private:
233
234 CommMonitor& mon;
235
236 };
237
238 /** Instance of slave port, i.e. on the CPU side */
239 MonitorSlavePort slavePort;
240
241 void recvFunctional(PacketPtr pkt);
242
243 void recvFunctionalSnoop(PacketPtr pkt);
244
245 Tick recvAtomic(PacketPtr pkt);
246
247 Tick recvAtomicSnoop(PacketPtr pkt);
248
249 bool recvTimingReq(PacketPtr pkt);
250
251 bool recvTimingResp(PacketPtr pkt);
252
253 void recvTimingSnoopReq(PacketPtr pkt);
254
255 bool recvTimingSnoopResp(PacketPtr pkt);
256
257 AddrRangeList getAddrRanges() const;
258
259 bool isSnooping() const;
260
261 void recvReqRetry();
262
263 void recvRespRetry();
264
265 void recvRangeChange();
266
267 /** Stats declarations, all in a struct for convenience. */
268 struct MonitorStats
269 {
270
271 /** Disable flag for burst length historgrams **/
272 bool disableBurstLengthHists;
273
274 /** Histogram of read burst lengths */
275 Stats::Histogram readBurstLengthHist;
276
277 /** Histogram of write burst lengths */
278 Stats::Histogram writeBurstLengthHist;
279
280 /** Disable flag for the bandwidth histograms */
281 bool disableBandwidthHists;
282
283 /**
284 * Histogram for read bandwidth per sample window. The
285 * internal counter is an unsigned int rather than a stat.
286 */
287 unsigned int readBytes;
288 Stats::Histogram readBandwidthHist;
289 Stats::Formula averageReadBW;
290 Stats::Scalar totalReadBytes;
291
292 /**
293 * Histogram for write bandwidth per sample window. The
294 * internal counter is an unsigned int rather than a stat.
295 */
296 unsigned int writtenBytes;
297 Stats::Histogram writeBandwidthHist;
298 Stats::Formula averageWriteBW;
299 Stats::Scalar totalWrittenBytes;
300
301 /** Disable flag for latency histograms. */
302 bool disableLatencyHists;
303
304 /** Histogram of read request-to-response latencies */
305 Stats::Histogram readLatencyHist;
306
307 /** Histogram of write request-to-response latencies */
308 Stats::Histogram writeLatencyHist;
309
310 /** Disable flag for ITT distributions. */
311 bool disableITTDists;
312
313 /**
314 * Inter transaction time (ITT) distributions. There are
315 * histograms of the time between two read, write or arbitrary
316 * accesses. The time of a request is the tick at which the
317 * request is forwarded by the monitor.
318 */
319 Stats::Distribution ittReadRead;
320 Stats::Distribution ittWriteWrite;
321 Stats::Distribution ittReqReq;
322 Tick timeOfLastRead;
323 Tick timeOfLastWrite;
324 Tick timeOfLastReq;
325
326 /** Disable flag for outstanding histograms. */
327 bool disableOutstandingHists;
328
329 /**
330 * Histogram of outstanding read requests. Counter for
331 * outstanding read requests is an unsigned integer because
332 * it should not be reset when stats are reset.
333 */
334 Stats::Histogram outstandingReadsHist;
335 unsigned int outstandingReadReqs;
336
337 /**
338 * Histogram of outstanding write requests. Counter for
339 * outstanding write requests is an unsigned integer because
340 * it should not be reset when stats are reset.
341 */
342 Stats::Histogram outstandingWritesHist;
343 unsigned int outstandingWriteReqs;
344
345 /** Disable flag for transaction histograms. */
346 bool disableTransactionHists;
347
348 /** Histogram of number of read transactions per time bin */
349 Stats::Histogram readTransHist;
350 unsigned int readTrans;
351
352 /** Histogram of number of timing write transactions per time bin */
353 Stats::Histogram writeTransHist;
354 unsigned int writeTrans;
355
356 /** Disable flag for address distributions. */
357 bool disableAddrDists;
358
359 /**
360 * Histogram of number of read accesses to addresses over
361 * time.
362 */
363 Stats::SparseHistogram readAddrDist;
364
365 /**
366 * Histogram of number of write accesses to addresses over
367 * time.
368 */
369 Stats::SparseHistogram writeAddrDist;
370
371 /**
372 * Create the monitor stats and initialise all the members
373 * that are not statistics themselves, but used to control the
374 * stats or track values during a sample period.
375 */
376 MonitorStats(const CommMonitorParams* params) :
377 disableBurstLengthHists(params->disable_burst_length_hists),
378 disableBandwidthHists(params->disable_bandwidth_hists),
379 readBytes(0), writtenBytes(0),
380 disableLatencyHists(params->disable_latency_hists),
381 disableITTDists(params->disable_itt_dists),
382 timeOfLastRead(0), timeOfLastWrite(0), timeOfLastReq(0),
383 disableOutstandingHists(params->disable_outstanding_hists),
384 outstandingReadReqs(0), outstandingWriteReqs(0),
385 disableTransactionHists(params->disable_transaction_hists),
386 readTrans(0), writeTrans(0),
387 disableAddrDists(params->disable_addr_dists)
388 { }
389
390 };
391
392 /** This function is called periodically at the end of each time bin */
393 void samplePeriodic();
394
395 /**
396 * Callback to flush and close all open output streams on exit. If
397 * we were calling the destructor it could be done there.
398 */
399 void closeStreams();
400
401 /** Periodic event called at the end of each simulation time bin */
402 EventWrapper<CommMonitor, &CommMonitor::samplePeriodic> samplePeriodicEvent;
403
404 /**
405 *@{
406 * @name Configuration
407 */
408
409 /** Length of simulation time bin*/
410 const Tick samplePeriodTicks;
411 /** Sample period in seconds */
412 const double samplePeriod;
413
414 /** Address mask for sources of read accesses to be captured */
415 const Addr readAddrMask;
416
417 /** Address mask for sources of write accesses to be captured */
418 const Addr writeAddrMask;
419
420 /** Optional stack distance calculator */
421 StackDistCalc *const stackDistCalc;
422
423 /** The system in which the monitor lives */
424 System *const system;
425
426 /** @} */
427
428 /** Output stream for a potential trace. */
429 ProtoOutputStream *traceStream;
430
431 /** Instantiate stats */
432 MonitorStats stats;
433
434 protected: // Probe points
435 /**
436 * @{
437 * @name Memory system probe points
438 */
439
440 /** Successfully forwarded request packet */
441 ProbePoints::PacketUPtr ppPktReq;
442
443 /** Successfully forwarded response packet */
444 ProbePoints::PacketUPtr ppPktResp;
445
446 /** @} */
447};
448
449#endif //__MEM_COMM_MONITOR_HH__