1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 130 unchanged lines hidden (view full) --- 139 140 // Store relevant fields of packet, because packet may be modified 141 // or even deleted when sendTiming() is called. 142 const ProbePoints::PacketInfo pkt_info(pkt); 143 144 const bool is_read = pkt->isRead(); 145 const bool is_write = pkt->isWrite(); 146 const bool expects_response( |
147 pkt->needsResponse() && !pkt->cacheResponding()); |
148 149 // If a cache miss is served by a cache, a monitor near the memory 150 // would see a request which needs a response, but this response |
151 // would not come back from the memory. Therefore we additionally 152 // have to check the cacheResponding flag |
153 if (expects_response && !stats.disableLatencyHists) { 154 pkt->pushSenderState(new CommMonitorSenderState(curTick())); 155 } 156 |
157 // Attempt to send the packet |
158 bool successful = masterPort.sendTimingReq(pkt); 159 160 // If not successful, restore the sender state 161 if (!successful && expects_response && !stats.disableLatencyHists) { 162 delete pkt->popSenderState(); 163 } 164 165 if (successful) { --- 387 unchanged lines hidden --- |