coherent_xbar.cc (12345:70c783a93195) coherent_xbar.cc (12346:9b1144d046ca)
1/*
2 * Copyright (c) 2011-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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178 Tick xbar_delay = (frontendLatency + forwardLatency) * clockPeriod();
179
180 // set the packet header and payload delay
181 calcPacketTiming(pkt, xbar_delay);
182
183 // determine how long to be crossbar layer is busy
184 Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
185
1/*
2 * Copyright (c) 2011-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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178 Tick xbar_delay = (frontendLatency + forwardLatency) * clockPeriod();
179
180 // set the packet header and payload delay
181 calcPacketTiming(pkt, xbar_delay);
182
183 // determine how long to be crossbar layer is busy
184 Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
185
186 // is this the destination point for this packet? (e.g. true if
187 // this xbar is the PoC for a cache maintenance operation to the
188 // PoC) otherwise the destination is any cache that can satisfy
189 // the request
190 const bool is_destination = isDestination(pkt);
191
186 const bool snoop_caches = !system->bypassCaches() &&
187 pkt->cmd != MemCmd::WriteClean;
188 if (snoop_caches) {
189 assert(pkt->snoopDelay == 0);
190
191 // the packet is a memory-mapped request and should be
192 // broadcasted to our snoopers but the source
193 if (snoopFilter) {

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238 // modify the address upon a sendTimingRequest
239 const Addr addr(pkt->getAddr());
240 if (sink_packet) {
241 DPRINTF(CoherentXBar, "%s: Not forwarding %s\n", __func__,
242 pkt->print());
243 } else {
244 // determine if we are forwarding the packet, or responding to
245 // it
192 const bool snoop_caches = !system->bypassCaches() &&
193 pkt->cmd != MemCmd::WriteClean;
194 if (snoop_caches) {
195 assert(pkt->snoopDelay == 0);
196
197 // the packet is a memory-mapped request and should be
198 // broadcasted to our snoopers but the source
199 if (snoopFilter) {

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244 // modify the address upon a sendTimingRequest
245 const Addr addr(pkt->getAddr());
246 if (sink_packet) {
247 DPRINTF(CoherentXBar, "%s: Not forwarding %s\n", __func__,
248 pkt->print());
249 } else {
250 // determine if we are forwarding the packet, or responding to
251 // it
246 if (!pointOfCoherency || pkt->isRead() || pkt->isWrite()) {
252 if (forwardPacket(pkt)) {
247 // if we are passing on, rather than sinking, a packet to
248 // which an upstream cache has committed to responding,
249 // the line was needs writable, and the responding only
250 // had an Owned copy, so we need to immidiately let the
251 // downstream caches know, bypass any flow control
252 if (pkt->cacheResponding()) {
253 pkt->setExpressSnoop();
254 }
255
253 // if we are passing on, rather than sinking, a packet to
254 // which an upstream cache has committed to responding,
255 // the line was needs writable, and the responding only
256 // had an Owned copy, so we need to immidiately let the
257 // downstream caches know, bypass any flow control
258 if (pkt->cacheResponding()) {
259 pkt->setExpressSnoop();
260 }
261
262 // make sure that the write request (e.g., WriteClean)
263 // will stop at the memory below if this crossbar is its
264 // destination
265 if (pkt->isWrite() && is_destination) {
266 pkt->clearWriteThrough();
267 }
268
256 // since it is a normal request, attempt to send the packet
257 success = masterPorts[master_port_id]->sendTimingReq(pkt);
258 } else {
259 // no need to forward, turn this packet around and respond
260 // directly
261 assert(pkt->needsResponse());
262
263 respond_directly = true;

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641 slavePorts[slave_port_id]->name(), pkt->print());
642
643 unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
644 unsigned int pkt_cmd = pkt->cmdToIndex();
645
646 MemCmd snoop_response_cmd = MemCmd::InvalidCmd;
647 Tick snoop_response_latency = 0;
648
269 // since it is a normal request, attempt to send the packet
270 success = masterPorts[master_port_id]->sendTimingReq(pkt);
271 } else {
272 // no need to forward, turn this packet around and respond
273 // directly
274 assert(pkt->needsResponse());
275
276 respond_directly = true;

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654 slavePorts[slave_port_id]->name(), pkt->print());
655
656 unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
657 unsigned int pkt_cmd = pkt->cmdToIndex();
658
659 MemCmd snoop_response_cmd = MemCmd::InvalidCmd;
660 Tick snoop_response_latency = 0;
661
662 // is this the destination point for this packet? (e.g. true if
663 // this xbar is the PoC for a cache maintenance operation to the
664 // PoC) otherwise the destination is any cache that can satisfy
665 // the request
666 const bool is_destination = isDestination(pkt);
667
649 const bool snoop_caches = !system->bypassCaches() &&
650 pkt->cmd != MemCmd::WriteClean;
651 if (snoop_caches) {
652 // forward to all snoopers but the source
653 std::pair<MemCmd, Tick> snoop_result;
654 if (snoopFilter) {
655 // check with the snoop filter where to forward this packet
656 auto sf_res =

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693 // even if we had a snoop response, we must continue and also
694 // perform the actual request at the destination
695 PortID master_port_id = findPort(pkt->getAddr());
696
697 if (sink_packet) {
698 DPRINTF(CoherentXBar, "%s: Not forwarding %s\n", __func__,
699 pkt->print());
700 } else {
668 const bool snoop_caches = !system->bypassCaches() &&
669 pkt->cmd != MemCmd::WriteClean;
670 if (snoop_caches) {
671 // forward to all snoopers but the source
672 std::pair<MemCmd, Tick> snoop_result;
673 if (snoopFilter) {
674 // check with the snoop filter where to forward this packet
675 auto sf_res =

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712 // even if we had a snoop response, we must continue and also
713 // perform the actual request at the destination
714 PortID master_port_id = findPort(pkt->getAddr());
715
716 if (sink_packet) {
717 DPRINTF(CoherentXBar, "%s: Not forwarding %s\n", __func__,
718 pkt->print());
719 } else {
701 if (!pointOfCoherency || pkt->isRead() || pkt->isWrite()) {
720 if (forwardPacket(pkt)) {
721 // make sure that the write request (e.g., WriteClean)
722 // will stop at the memory below if this crossbar is its
723 // destination
724 if (pkt->isWrite() && is_destination) {
725 pkt->clearWriteThrough();
726 }
727
702 // forward the request to the appropriate destination
703 response_latency = masterPorts[master_port_id]->sendAtomic(pkt);
704 } else {
705 // if it does not need a response we sink the packet above
706 assert(pkt->needsResponse());
707
708 pkt->makeResponse();
709 }

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953 return (pointOfCoherency && pkt->cacheResponding()) ||
954 (pointOfCoherency && !(pkt->isRead() || pkt->isWrite()) &&
955 !pkt->needsResponse()) ||
956 (pkt->isCleanEviction() && pkt->isBlockCached()) ||
957 (pkt->cacheResponding() &&
958 (!pkt->needsWritable() || pkt->responderHadWritable()));
959}
960
728 // forward the request to the appropriate destination
729 response_latency = masterPorts[master_port_id]->sendAtomic(pkt);
730 } else {
731 // if it does not need a response we sink the packet above
732 assert(pkt->needsResponse());
733
734 pkt->makeResponse();
735 }

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979 return (pointOfCoherency && pkt->cacheResponding()) ||
980 (pointOfCoherency && !(pkt->isRead() || pkt->isWrite()) &&
981 !pkt->needsResponse()) ||
982 (pkt->isCleanEviction() && pkt->isBlockCached()) ||
983 (pkt->cacheResponding() &&
984 (!pkt->needsWritable() || pkt->responderHadWritable()));
985}
986
987bool
988CoherentXBar::forwardPacket(const PacketPtr pkt)
989{
990 // we are forwarding the packet if:
991 // 1) this is a read or a write
992 // 2) this crossbar is above the point of coherency
993 return pkt->isRead() || pkt->isWrite() || !pointOfCoherency;
994}
995
996
961void
962CoherentXBar::regStats()
963{
964 // register the stats of the base class and our layers
965 BaseXBar::regStats();
966 for (auto l: reqLayers)
967 l->regStats();
968 for (auto l: respLayers)

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998CoherentXBar::regStats()
999{
1000 // register the stats of the base class and our layers
1001 BaseXBar::regStats();
1002 for (auto l: reqLayers)
1003 l->regStats();
1004 for (auto l: respLayers)

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