1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Andreas Hansson
42 */
43
44/**
45 * @file
46 * Write queue entry
47 */
48
49#ifndef __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
50#define __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
51
52#include <cassert>
53#include <iosfwd>
54#include <list>
55#include <string>
56
57#include "base/printable.hh"
58#include "base/types.hh"
59#include "mem/cache/queue_entry.hh"
60#include "mem/packet.hh"
61#include "sim/core.hh"
62
63class BaseCache;
64
65/**
66 * Write queue entry
67 */
68class WriteQueueEntry : public QueueEntry, public Printable
69{
70
71 /**
72 * Consider the queues friends to avoid making everything public.
73 */
74 template<typename Entry>
75 friend class Queue;
76 friend class WriteQueue;
77
78 public:
79
80 class Target {
81 public:
82
83 const Tick recvTime; //!< Time when request was received (for stats)
84 const Tick readyTime; //!< Time when request is ready to be serviced
85 const Counter order; //!< Global order (for memory consistency mgmt)
86 const PacketPtr pkt; //!< Pending request packet.
87
88 Target(PacketPtr _pkt, Tick _readyTime, Counter _order)
89 : recvTime(curTick()), readyTime(_readyTime), order(_order),
90 pkt(_pkt)
91 {}
92 };
93
94 class TargetList : public std::list<Target> {
95
96 public:
97
98 TargetList() {}
99 void add(PacketPtr pkt, Tick readyTime, Counter order);
| 1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Andreas Hansson
42 */
43
44/**
45 * @file
46 * Write queue entry
47 */
48
49#ifndef __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
50#define __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
51
52#include <cassert>
53#include <iosfwd>
54#include <list>
55#include <string>
56
57#include "base/printable.hh"
58#include "base/types.hh"
59#include "mem/cache/queue_entry.hh"
60#include "mem/packet.hh"
61#include "sim/core.hh"
62
63class BaseCache;
64
65/**
66 * Write queue entry
67 */
68class WriteQueueEntry : public QueueEntry, public Printable
69{
70
71 /**
72 * Consider the queues friends to avoid making everything public.
73 */
74 template<typename Entry>
75 friend class Queue;
76 friend class WriteQueue;
77
78 public:
79
80 class Target {
81 public:
82
83 const Tick recvTime; //!< Time when request was received (for stats)
84 const Tick readyTime; //!< Time when request is ready to be serviced
85 const Counter order; //!< Global order (for memory consistency mgmt)
86 const PacketPtr pkt; //!< Pending request packet.
87
88 Target(PacketPtr _pkt, Tick _readyTime, Counter _order)
89 : recvTime(curTick()), readyTime(_readyTime), order(_order),
90 pkt(_pkt)
91 {}
92 };
93
94 class TargetList : public std::list<Target> {
95
96 public:
97
98 TargetList() {}
99 void add(PacketPtr pkt, Tick readyTime, Counter order);
|
101 void print(std::ostream &os, int verbosity,
102 const std::string &prefix) const;
103 };
104
105 /** A list of write queue entriess. */
106 typedef std::list<WriteQueueEntry *> List;
107 /** WriteQueueEntry list iterator. */
108 typedef List::iterator Iterator;
109
110 bool sendPacket(BaseCache &cache);
111
112 private:
113
114 /**
115 * Pointer to this entry on the ready list.
116 * @sa MissQueue, WriteQueue::readyList
117 */
118 Iterator readyIter;
119
120 /**
121 * Pointer to this entry on the allocated list.
122 * @sa MissQueue, WriteQueue::allocatedList
123 */
124 Iterator allocIter;
125
126 /** List of all requests that match the address */
127 TargetList targets;
128
129 public:
130
131 /** A simple constructor. */
132 WriteQueueEntry() {}
133
134 /**
135 * Allocate a miss to this entry.
136 * @param blk_addr The address of the block.
137 * @param blk_size The number of bytes to request.
138 * @param pkt The original write.
139 * @param when_ready When should the write be sent out.
140 * @param _order The logical order of this write.
141 */
142 void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
143 Tick when_ready, Counter _order);
144
145
146 /**
147 * Mark this entry as free.
148 */
149 void deallocate();
150
151 /**
152 * Returns the current number of allocated targets.
153 * @return The current number of allocated targets.
154 */
155 int getNumTargets() const
156 { return targets.size(); }
157
158 /**
159 * Returns true if there are targets left.
160 * @return true if there are targets
161 */
162 bool hasTargets() const { return !targets.empty(); }
163
164 /**
165 * Returns a reference to the first target.
166 * @return A pointer to the first target.
167 */
168 Target *getTarget()
169 {
170 assert(hasTargets());
171 return &targets.front();
172 }
173
174 /**
175 * Pop first target.
176 */
177 void popTarget()
178 {
179 targets.pop_front();
180 }
181
| 101 void print(std::ostream &os, int verbosity,
102 const std::string &prefix) const;
103 };
104
105 /** A list of write queue entriess. */
106 typedef std::list<WriteQueueEntry *> List;
107 /** WriteQueueEntry list iterator. */
108 typedef List::iterator Iterator;
109
110 bool sendPacket(BaseCache &cache);
111
112 private:
113
114 /**
115 * Pointer to this entry on the ready list.
116 * @sa MissQueue, WriteQueue::readyList
117 */
118 Iterator readyIter;
119
120 /**
121 * Pointer to this entry on the allocated list.
122 * @sa MissQueue, WriteQueue::allocatedList
123 */
124 Iterator allocIter;
125
126 /** List of all requests that match the address */
127 TargetList targets;
128
129 public:
130
131 /** A simple constructor. */
132 WriteQueueEntry() {}
133
134 /**
135 * Allocate a miss to this entry.
136 * @param blk_addr The address of the block.
137 * @param blk_size The number of bytes to request.
138 * @param pkt The original write.
139 * @param when_ready When should the write be sent out.
140 * @param _order The logical order of this write.
141 */
142 void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
143 Tick when_ready, Counter _order);
144
145
146 /**
147 * Mark this entry as free.
148 */
149 void deallocate();
150
151 /**
152 * Returns the current number of allocated targets.
153 * @return The current number of allocated targets.
154 */
155 int getNumTargets() const
156 { return targets.size(); }
157
158 /**
159 * Returns true if there are targets left.
160 * @return true if there are targets
161 */
162 bool hasTargets() const { return !targets.empty(); }
163
164 /**
165 * Returns a reference to the first target.
166 * @return A pointer to the first target.
167 */
168 Target *getTarget()
169 {
170 assert(hasTargets());
171 return &targets.front();
172 }
173
174 /**
175 * Pop first target.
176 */
177 void popTarget()
178 {
179 targets.pop_front();
180 }
181
|