1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Andreas Hansson
42 */
43
44/**
45 * @file
46 * Write queue entry
47 */
48
49#ifndef __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
50#define __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
51
52#include <list>
53
54#include "base/printable.hh"
55#include "mem/cache/queue_entry.hh"
56
| 1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Andreas Hansson
42 */
43
44/**
45 * @file
46 * Write queue entry
47 */
48
49#ifndef __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
50#define __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
51
52#include <list>
53
54#include "base/printable.hh"
55#include "mem/cache/queue_entry.hh"
56
|
57class Cache;
| 57class BaseCache;
|
58
59/**
60 * Write queue entry
61 */
62class WriteQueueEntry : public QueueEntry, public Printable
63{
64
65 /**
66 * Consider the queues friends to avoid making everything public.
67 */
68 template<typename Entry>
69 friend class Queue;
70 friend class WriteQueue;
71
72 public:
73
74 class Target {
75 public:
76
77 const Tick recvTime; //!< Time when request was received (for stats)
78 const Tick readyTime; //!< Time when request is ready to be serviced
79 const Counter order; //!< Global order (for memory consistency mgmt)
80 const PacketPtr pkt; //!< Pending request packet.
81
82 Target(PacketPtr _pkt, Tick _readyTime, Counter _order)
83 : recvTime(curTick()), readyTime(_readyTime), order(_order),
84 pkt(_pkt)
85 {}
86 };
87
88 class TargetList : public std::list<Target> {
89
90 public:
91
92 TargetList() {}
93 void add(PacketPtr pkt, Tick readyTime, Counter order);
94 bool checkFunctional(PacketPtr pkt);
95 void print(std::ostream &os, int verbosity,
96 const std::string &prefix) const;
97 };
98
99 /** A list of write queue entriess. */
100 typedef std::list<WriteQueueEntry *> List;
101 /** WriteQueueEntry list iterator. */
102 typedef List::iterator Iterator;
103
| 58
59/**
60 * Write queue entry
61 */
62class WriteQueueEntry : public QueueEntry, public Printable
63{
64
65 /**
66 * Consider the queues friends to avoid making everything public.
67 */
68 template<typename Entry>
69 friend class Queue;
70 friend class WriteQueue;
71
72 public:
73
74 class Target {
75 public:
76
77 const Tick recvTime; //!< Time when request was received (for stats)
78 const Tick readyTime; //!< Time when request is ready to be serviced
79 const Counter order; //!< Global order (for memory consistency mgmt)
80 const PacketPtr pkt; //!< Pending request packet.
81
82 Target(PacketPtr _pkt, Tick _readyTime, Counter _order)
83 : recvTime(curTick()), readyTime(_readyTime), order(_order),
84 pkt(_pkt)
85 {}
86 };
87
88 class TargetList : public std::list<Target> {
89
90 public:
91
92 TargetList() {}
93 void add(PacketPtr pkt, Tick readyTime, Counter order);
94 bool checkFunctional(PacketPtr pkt);
95 void print(std::ostream &os, int verbosity,
96 const std::string &prefix) const;
97 };
98
99 /** A list of write queue entriess. */
100 typedef std::list<WriteQueueEntry *> List;
101 /** WriteQueueEntry list iterator. */
102 typedef List::iterator Iterator;
103
|
104 bool sendPacket(Cache &cache);
| 104 bool sendPacket(BaseCache &cache);
|
105
106 private:
107
108 /**
109 * Pointer to this entry on the ready list.
110 * @sa MissQueue, WriteQueue::readyList
111 */
112 Iterator readyIter;
113
114 /**
115 * Pointer to this entry on the allocated list.
116 * @sa MissQueue, WriteQueue::allocatedList
117 */
118 Iterator allocIter;
119
120 /** List of all requests that match the address */
121 TargetList targets;
122
123 public:
124
125 /** A simple constructor. */
126 WriteQueueEntry() {}
127
128 /**
129 * Allocate a miss to this entry.
130 * @param blk_addr The address of the block.
131 * @param blk_size The number of bytes to request.
132 * @param pkt The original write.
133 * @param when_ready When should the write be sent out.
134 * @param _order The logical order of this write.
135 */
136 void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
137 Tick when_ready, Counter _order);
138
139
140 /**
141 * Mark this entry as free.
142 */
143 void deallocate();
144
145 /**
146 * Returns the current number of allocated targets.
147 * @return The current number of allocated targets.
148 */
149 int getNumTargets() const
150 { return targets.size(); }
151
152 /**
153 * Returns true if there are targets left.
154 * @return true if there are targets
155 */
156 bool hasTargets() const { return !targets.empty(); }
157
158 /**
159 * Returns a reference to the first target.
160 * @return A pointer to the first target.
161 */
162 Target *getTarget()
163 {
164 assert(hasTargets());
165 return &targets.front();
166 }
167
168 /**
169 * Pop first target.
170 */
171 void popTarget()
172 {
173 targets.pop_front();
174 }
175
176 bool checkFunctional(PacketPtr pkt);
177
178 /**
179 * Prints the contents of this MSHR for debugging.
180 */
181 void print(std::ostream &os,
182 int verbosity = 0,
183 const std::string &prefix = "") const;
184 /**
185 * A no-args wrapper of print(std::ostream...) meant to be
186 * invoked from DPRINTFs avoiding string overheads in fast mode
187 *
188 * @return string with mshr fields
189 */
190 std::string print() const;
191};
192
193#endif // __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
| 105
106 private:
107
108 /**
109 * Pointer to this entry on the ready list.
110 * @sa MissQueue, WriteQueue::readyList
111 */
112 Iterator readyIter;
113
114 /**
115 * Pointer to this entry on the allocated list.
116 * @sa MissQueue, WriteQueue::allocatedList
117 */
118 Iterator allocIter;
119
120 /** List of all requests that match the address */
121 TargetList targets;
122
123 public:
124
125 /** A simple constructor. */
126 WriteQueueEntry() {}
127
128 /**
129 * Allocate a miss to this entry.
130 * @param blk_addr The address of the block.
131 * @param blk_size The number of bytes to request.
132 * @param pkt The original write.
133 * @param when_ready When should the write be sent out.
134 * @param _order The logical order of this write.
135 */
136 void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
137 Tick when_ready, Counter _order);
138
139
140 /**
141 * Mark this entry as free.
142 */
143 void deallocate();
144
145 /**
146 * Returns the current number of allocated targets.
147 * @return The current number of allocated targets.
148 */
149 int getNumTargets() const
150 { return targets.size(); }
151
152 /**
153 * Returns true if there are targets left.
154 * @return true if there are targets
155 */
156 bool hasTargets() const { return !targets.empty(); }
157
158 /**
159 * Returns a reference to the first target.
160 * @return A pointer to the first target.
161 */
162 Target *getTarget()
163 {
164 assert(hasTargets());
165 return &targets.front();
166 }
167
168 /**
169 * Pop first target.
170 */
171 void popTarget()
172 {
173 targets.pop_front();
174 }
175
176 bool checkFunctional(PacketPtr pkt);
177
178 /**
179 * Prints the contents of this MSHR for debugging.
180 */
181 void print(std::ostream &os,
182 int verbosity = 0,
183 const std::string &prefix = "") const;
184 /**
185 * A no-args wrapper of print(std::ostream...) meant to be
186 * invoked from DPRINTFs avoiding string overheads in fast mode
187 *
188 * @return string with mshr fields
189 */
190 std::string print() const;
191};
192
193#endif // __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
|