write_queue_entry.cc (12724:4f6fac3191d2) write_queue_entry.cc (12727:56c23b54bcb1)
1/*
2 * Copyright (c) 2012-2013, 2015-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45
46/**
47 * @file
48 * Miss Status and Handling Register (WriteQueueEntry) definitions.
49 */
50
51#include "mem/cache/write_queue_entry.hh"
52
1/*
2 * Copyright (c) 2012-2013, 2015-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45
46/**
47 * @file
48 * Miss Status and Handling Register (WriteQueueEntry) definitions.
49 */
50
51#include "mem/cache/write_queue_entry.hh"
52
53#include <algorithm>
54#include <cassert>
55#include <string>
53#include <cassert>
54#include <string>
56#include <vector>
57
58#include "base/logging.hh"
59#include "base/types.hh"
55
56#include "base/logging.hh"
57#include "base/types.hh"
60#include "debug/Cache.hh"
61#include "mem/cache/cache.hh"
62#include "sim/core.hh"
58#include "mem/cache/base.hh"
59#include "mem/request.hh"
63
64inline void
65WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
66 Counter order)
67{
68 emplace_back(pkt, readyTime, order);
69}
70

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61inline void
62WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
63 Counter order)
64{
65 emplace_back(pkt, readyTime, order);
66}
67

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