1/* 2 * Copyright (c) 2012-2013, 2015-2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 36 unchanged lines hidden (view full) --- 45 46/** 47 * @file 48 * Miss Status and Handling Register (WriteQueueEntry) definitions. 49 */ 50 51#include "mem/cache/write_queue_entry.hh" 52 |
53#include <cassert> 54#include <string> |
55 56#include "base/logging.hh" 57#include "base/types.hh" |
58#include "mem/cache/base.hh" 59#include "mem/request.hh" |
60 61inline void 62WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime, 63 Counter order) 64{ 65 emplace_back(pkt, readyTime, order); 66} 67 --- 97 unchanged lines hidden --- |