1/* 2 * Copyright (c) 2012-2013, 2015-2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 47 unchanged lines hidden (view full) --- 56#include <vector> 57 58#include "base/logging.hh" 59#include "base/types.hh" 60#include "debug/Cache.hh" 61#include "mem/cache/cache.hh" 62#include "sim/core.hh" 63 |
64inline void 65WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime, 66 Counter order) 67{ 68 emplace_back(pkt, readyTime, order); 69} 70 71bool --- 84 unchanged lines hidden (view full) --- 156 157 ccprintf(os, "%s Targets:\n", prefix); 158 targets.print(os, verbosity, prefix + " "); 159} 160 161std::string 162WriteQueueEntry::print() const 163{ |
164 std::ostringstream str; |
165 print(str); 166 return str.str(); 167} |