1/*
2 * Copyright (c) 2012-2013, 2015-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Erik Hallnor
42 * Dave Greene
43 * Andreas Hansson
44 */
45
46/**
47 * @file
48 * Miss Status and Handling Register (WriteQueueEntry) definitions.
49 */
50
51#include "mem/cache/write_queue_entry.hh"
52
| 1/*
2 * Copyright (c) 2012-2013, 2015-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Erik Hallnor
42 * Dave Greene
43 * Andreas Hansson
44 */
45
46/**
47 * @file
48 * Miss Status and Handling Register (WriteQueueEntry) definitions.
49 */
50
51#include "mem/cache/write_queue_entry.hh"
52
|
63
64inline void
65WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
66 Counter order)
67{
68 emplace_back(pkt, readyTime, order);
69}
70
71bool
72WriteQueueEntry::TargetList::checkFunctional(PacketPtr pkt)
73{
74 for (auto& t : *this) {
75 if (pkt->checkFunctional(t.pkt)) {
76 return true;
77 }
78 }
79
80 return false;
81}
82
83void
84WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
85 const std::string &prefix) const
86{
87 for (auto& t : *this) {
88 ccprintf(os, "%sFromCPU: ", prefix);
89 t.pkt->print(os, verbosity, "");
90 }
91}
92
93void
94WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
95 Tick when_ready, Counter _order)
96{
97 blkAddr = blk_addr;
98 blkSize = blk_size;
99 isSecure = target->isSecure();
100 readyTime = when_ready;
101 order = _order;
102 assert(target);
103 _isUncacheable = target->req->isUncacheable();
104 inService = false;
105
106 // we should never have more than a single target for cacheable
107 // writes (writebacks and clean evictions)
108 panic_if(!_isUncacheable && !targets.empty(),
109 "Write queue entry %#llx should never have more than one "
110 "cacheable target", blkAddr);
111 panic_if(!((target->isWrite() && _isUncacheable) ||
112 (target->isEviction() && !_isUncacheable) ||
113 target->cmd == MemCmd::WriteClean),
114 "Write queue entry %#llx should be an uncacheable write or "
115 "a cacheable eviction or a writeclean");
116
117 targets.add(target, when_ready, _order);
118}
119
120void
121WriteQueueEntry::deallocate()
122{
123 assert(targets.empty());
124 inService = false;
125}
126
127bool
128WriteQueueEntry::checkFunctional(PacketPtr pkt)
129{
130 // For printing, we treat the WriteQueueEntry as a whole as single
131 // entity. For other requests, we iterate over the individual
132 // targets since that's where the actual data lies.
133 if (pkt->isPrint()) {
134 pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
135 return false;
136 } else {
137 return targets.checkFunctional(pkt);
138 }
139}
140
141bool
142WriteQueueEntry::sendPacket(BaseCache &cache)
143{
144 return cache.sendWriteQueuePacket(this);
145}
146
147void
148WriteQueueEntry::print(std::ostream &os, int verbosity,
149 const std::string &prefix) const
150{
151 ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
152 prefix, blkAddr, blkAddr + blkSize - 1,
153 isSecure ? "s" : "ns",
154 _isUncacheable ? "Unc" : "",
155 inService ? "InSvc" : "");
156
157 ccprintf(os, "%s Targets:\n", prefix);
158 targets.print(os, verbosity, prefix + " ");
159}
160
161std::string
162WriteQueueEntry::print() const
163{
164 std::ostringstream str;
165 print(str);
166 return str.str();
167}
| 60
61inline void
62WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
63 Counter order)
64{
65 emplace_back(pkt, readyTime, order);
66}
67
68bool
69WriteQueueEntry::TargetList::checkFunctional(PacketPtr pkt)
70{
71 for (auto& t : *this) {
72 if (pkt->checkFunctional(t.pkt)) {
73 return true;
74 }
75 }
76
77 return false;
78}
79
80void
81WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
82 const std::string &prefix) const
83{
84 for (auto& t : *this) {
85 ccprintf(os, "%sFromCPU: ", prefix);
86 t.pkt->print(os, verbosity, "");
87 }
88}
89
90void
91WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
92 Tick when_ready, Counter _order)
93{
94 blkAddr = blk_addr;
95 blkSize = blk_size;
96 isSecure = target->isSecure();
97 readyTime = when_ready;
98 order = _order;
99 assert(target);
100 _isUncacheable = target->req->isUncacheable();
101 inService = false;
102
103 // we should never have more than a single target for cacheable
104 // writes (writebacks and clean evictions)
105 panic_if(!_isUncacheable && !targets.empty(),
106 "Write queue entry %#llx should never have more than one "
107 "cacheable target", blkAddr);
108 panic_if(!((target->isWrite() && _isUncacheable) ||
109 (target->isEviction() && !_isUncacheable) ||
110 target->cmd == MemCmd::WriteClean),
111 "Write queue entry %#llx should be an uncacheable write or "
112 "a cacheable eviction or a writeclean");
113
114 targets.add(target, when_ready, _order);
115}
116
117void
118WriteQueueEntry::deallocate()
119{
120 assert(targets.empty());
121 inService = false;
122}
123
124bool
125WriteQueueEntry::checkFunctional(PacketPtr pkt)
126{
127 // For printing, we treat the WriteQueueEntry as a whole as single
128 // entity. For other requests, we iterate over the individual
129 // targets since that's where the actual data lies.
130 if (pkt->isPrint()) {
131 pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
132 return false;
133 } else {
134 return targets.checkFunctional(pkt);
135 }
136}
137
138bool
139WriteQueueEntry::sendPacket(BaseCache &cache)
140{
141 return cache.sendWriteQueuePacket(this);
142}
143
144void
145WriteQueueEntry::print(std::ostream &os, int verbosity,
146 const std::string &prefix) const
147{
148 ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
149 prefix, blkAddr, blkAddr + blkSize - 1,
150 isSecure ? "s" : "ns",
151 _isUncacheable ? "Unc" : "",
152 inService ? "InSvc" : "");
153
154 ccprintf(os, "%s Targets:\n", prefix);
155 targets.print(os, verbosity, prefix + " ");
156}
157
158std::string
159WriteQueueEntry::print() const
160{
161 std::ostringstream str;
162 print(str);
163 return str.str();
164}
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