1/* 2 * Copyright (c) 2018 Inria 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 43 unchanged lines hidden (view full) --- 52 * @sa \ref gem5MemorySystem "gem5 Memory System" 53 * 54 * The SectorTags placement policy divides the cache into s sectors of w 55 * consecutive sectors (ways). Each sector then consists of a number of 56 * sequential cache lines that may or may not be present. 57 */ 58class SectorTags : public BaseTags 59{ |
60 private: 61 /** The cache blocks. */ 62 std::vector<SectorSubBlk> blks; 63 /** The cache sector blocks. */ 64 std::vector<SectorBlk> secBlks; 65 |
66 protected: 67 /** The allocatable associativity of the cache (alloc mask). */ 68 unsigned allocAssoc; 69 70 /** Whether tags and data are accessed sequentially. */ 71 const bool sequentialAccess; 72 73 /** Replacement policy */ 74 BaseReplacementPolicy *replacementPolicy; 75 76 /** Number of data blocks per sector. */ 77 const unsigned numBlocksPerSector; 78 79 /** The number of sectors in the cache. */ 80 const unsigned numSectors; 81 |
82 // Organization of an address: 83 // Tag | Placement Location | Sector Offset # | Offset # 84 /** The amount to shift the address to get the sector tag. */ 85 const int sectorShift; 86 87 /** Mask out all bits that aren't part of the sector tag. */ 88 const unsigned sectorMask; 89 --- 108 unchanged lines hidden --- |