1/* 2 * Copyright (c) 2018 Inria 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36#ifndef __MEM_CACHE_TAGS_SECTOR_TAGS_HH__ 37#define __MEM_CACHE_TAGS_SECTOR_TAGS_HH__ 38 39#include <string> 40#include <vector> 41 42#include "mem/cache/tags/base.hh" 43#include "mem/cache/tags/sector_blk.hh" |
44#include "mem/packet.hh" |
45#include "params/SectorTags.hh" 46 |
47class BaseReplacementPolicy; 48class ReplaceableEntry; 49 50/** 51 * A SectorTags cache tag store. 52 * @sa \ref gem5MemorySystem "gem5 Memory System" 53 * 54 * The SectorTags placement policy divides the cache into s sectors of w --- 69 unchanged lines hidden (view full) --- 124 * @param lat The latency of the tag lookup. 125 * @return Pointer to the cache block if found. 126 */ 127 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; 128 129 /** 130 * Insert the new block into the cache and update replacement data. 131 * |
132 * @param pkt Packet holding the address to update |
133 * @param blk The block to update. 134 */ |
135 void insertBlock(const PacketPtr pkt, CacheBlk *blk) override; |
136 137 /** 138 * Finds the given address in the cache, do not update replacement data. 139 * i.e. This is a no-side-effect find of a block. 140 * 141 * @param addr The address to find. 142 * @param is_secure True if the target memory space is secure. 143 * @return Pointer to the cache block if found. --- 53 unchanged lines hidden --- |