1/*
2 * Copyright (c) 2018 Inria
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52 * @sa \ref gem5MemorySystem "gem5 Memory System"
53 *
54 * The SectorTags placement policy divides the cache into s sectors of w
55 * consecutive sectors (ways). Each sector then consists of a number of
56 * sequential cache lines that may or may not be present.
57 */
58class SectorTags : public BaseTags
59{
60 protected:
61 /** The allocatable associativity of the cache (alloc mask). */
62 unsigned allocAssoc;
63
64 /** Whether tags and data are accessed sequentially. */
65 const bool sequentialAccess;
66
67 /** Replacement policy */
68 BaseReplacementPolicy *replacementPolicy;
69
70 /** Number of data blocks per sector. */
71 const unsigned numBlocksPerSector;
72
73 /** The number of sectors in the cache. */
74 const unsigned numSectors;
75
76 /** The cache blocks. */
77 std::vector<SectorSubBlk> blks;
78 /** The cache sector blocks. */
79 std::vector<SectorBlk> secBlks;
80
81 // Organization of an address:
82 // Tag | Placement Location | Sector Offset # | Offset #
83 /** The amount to shift the address to get the sector tag. */
84 const int sectorShift;
85
86 /** Mask out all bits that aren't part of the sector tag. */
87 const unsigned sectorMask;
88

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