1/*
2 * Copyright (c) 2018 Inria
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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40#include <vector>
41
42#include "mem/cache/sector_blk.hh"
43#include "mem/cache/tags/base.hh"
44#include "mem/packet.hh"
45#include "params/SectorTags.hh"
46
47class BaseReplacementPolicy;
48
49/**
50 * A SectorTags cache tag store.
51 * @sa \ref gem5MemorySystem "gem5 Memory System"
52 *
53 * The SectorTags placement policy divides the cache into s sectors of w
54 * consecutive sectors (ways). Each sector then consists of a number of
55 * sequential cache lines that may or may not be present.

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