1/* 2 * Copyright (c) 2012-2013,2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a fully associative LRU tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ 49#define __MEM_CACHE_TAGS_FA_LRU_HH__ 50 51#include <list> 52#include <unordered_map> 53 54#include "mem/cache/base.hh" 55#include "mem/cache/blk.hh" 56#include "mem/cache/tags/base.hh" 57#include "mem/packet.hh" 58#include "params/FALRU.hh" 59 60/** 61 * A fully associative cache block. 62 */ 63class FALRUBlk : public CacheBlk 64{ 65public: 66 /** The previous block in LRU order. */ 67 FALRUBlk *prev; 68 /** The next block in LRU order. */ 69 FALRUBlk *next; 70 /** Has this block been touched? */ 71 bool isTouched; 72 73 /** 74 * A bit mask of the sizes of cache that this block is resident in. 75 * Each bit represents a power of 2 in MB size cache. 76 * If bit 0 is set, this block is in a 1MB cache 77 * If bit 2 is set, this block is in a 4MB cache, etc. 78 * There is one bit for each cache smaller than the full size (default 79 * 16MB). 80 */ 81 int inCache; 82}; 83 84/** 85 * A fully associative LRU cache. Keeps statistics for accesses to a number of 86 * cache sizes at once. 87 */ 88class FALRU : public BaseTags 89{ 90 public: 91 /** Typedef the block type used in this class. */ 92 typedef FALRUBlk BlkType; 93 94 protected: 95 /** Array of pointers to blocks at the cache size boundaries. */ 96 FALRUBlk **cacheBoundaries; 97 /** A mask for the FALRUBlk::inCache bits. */ 98 int cacheMask; 99 /** The number of different size caches being tracked. */ 100 unsigned numCaches; 101 102 /** The cache blocks. */ 103 FALRUBlk *blks; 104 105 /** The MRU block. */ 106 FALRUBlk *head; 107 /** The LRU block. */ 108 FALRUBlk *tail; 109 110 /** Hash table type mapping addresses to cache block pointers. */ 111 typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t; 112 /** Iterator into the address hash table. */ 113 typedef hash_t::const_iterator tagIterator; 114 115 /** The address hash table. */ 116 hash_t tagHash; 117 118 /** 119 * Find the cache block for the given address. 120 * @param addr The address to find. 121 * @return The cache block of the address, if any. 122 */ 123 FALRUBlk * hashLookup(Addr addr) const; 124 125 /** 126 * Move a cache block to the MRU position. 127 * @param blk The block to promote. 128 */ 129 void moveToHead(FALRUBlk *blk); 130 131 /** 132 * Check to make sure all the cache boundaries are still where they should 133 * be. Used for debugging. 134 * @return True if everything is correct. 135 */ 136 bool check(); 137 138 /** 139 * @defgroup FALRUStats Fully Associative LRU specific statistics 140 * The FA lru stack lets us track multiple cache sizes at once. These 141 * statistics track the hits and misses for different cache sizes. 142 * @{ 143 */ 144 145 /** Hits in each cache size >= 128K. */ 146 Stats::Vector hits; 147 /** Misses in each cache size >= 128K. */ 148 Stats::Vector misses; 149 /** Total number of accesses. */ 150 Stats::Scalar accesses; 151 152 /** 153 * @} 154 */ 155 156public: 157 158 typedef FALRUParams Params; 159 160 /** 161 * Construct and initialize this cache tagstore. 162 */ 163 FALRU(const Params *p); 164 ~FALRU(); 165 166 /** 167 * Register the stats for this object. 168 * @param name The name to prepend to the stats name. 169 */ 170 void regStats() override; 171 172 /** 173 * Invalidate a cache block. 174 * @param blk The block to invalidate. 175 */ 176 void invalidate(CacheBlk *blk) override; 177 178 /** 179 * Access block and update replacement data. May not succeed, in which 180 * case nullptr pointer is returned. This has all the implications of a 181 * cache access and should only be used as such. 182 * Returns the access latency and inCache flags as a side effect. 183 * @param addr The address to look for. 184 * @param is_secure True if the target memory space is secure. 185 * @param lat The latency of the access. 186 * @param inCache The FALRUBlk::inCache flags. 187 * @return Pointer to the cache block. 188 */ 189 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 190 int *inCache); 191 192 /** 193 * Just a wrapper of above function to conform with the base interface. 194 */ 195 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; 196 197 /** 198 * Find the block in the cache, do not update the replacement data. 199 * @param addr The address to look for. 200 * @param is_secure True if the target memory space is secure. 201 * @param asid The address space ID. 202 * @return Pointer to the cache block. 203 */ 204 CacheBlk* findBlock(Addr addr, bool is_secure) const override; 205 206 /** 207 * Find a replacement block for the address provided. 208 * @param pkt The request to a find a replacement candidate for. 209 * @return The block to place the replacement in. 210 */ 211 CacheBlk* findVictim(Addr addr) override; 212 213 void insertBlock(PacketPtr pkt, CacheBlk *blk) override; 214 215 /** 216 * Find the cache block given set and way 217 * @param set The set of the block. 218 * @param way The way of the block. 219 * @return The cache block. 220 */ 221 CacheBlk* findBlockBySetAndWay(int set, int way) const override; 222 223 /** |
224 * Generate the tag from the addres. For fully associative this is just the 225 * block address. 226 * @param addr The address to get the tag from. 227 * @return The tag. 228 */ 229 Addr extractTag(Addr addr) const override 230 { 231 return blkAlign(addr); 232 } 233 234 /** 235 * Return the set of an address. Only one set in a fully associative cache. 236 * @param addr The address to get the set from. 237 * @return 0. 238 */ 239 int extractSet(Addr addr) const override 240 { 241 return 0; 242 } 243 244 /** 245 * Regenerate the block address from the tag and the set. 246 * @param tag The tag of the block. 247 * @param set The set the block belongs to. 248 * @return the block address. 249 */ 250 Addr regenerateBlkAddr(Addr tag, unsigned set) const override 251 { 252 return (tag); 253 } 254 255 /** 256 * @todo Implement as in lru. Currently not used 257 */ 258 virtual std::string print() const override { return ""; } 259 260 /** 261 * Visit each block in the tag store and apply a visitor to the 262 * block. 263 * 264 * The visitor should be a function (or object that behaves like a 265 * function) that takes a cache block reference as its parameter 266 * and returns a bool. A visitor can request the traversal to be 267 * stopped by returning false, returning true causes it to be 268 * called for the next block in the tag store. 269 * 270 * \param visitor Visitor to call on each block. 271 */ 272 void forEachBlk(CacheBlkVisitor &visitor) override { 273 for (int i = 0; i < numBlocks; i++) { 274 if (!visitor(blks[i])) 275 return; 276 } 277 } 278 279}; 280 281#endif // __MEM_CACHE_TAGS_FA_LRU_HH__ |