1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a fully associative LRU tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ 49#define __MEM_CACHE_TAGS_FA_LRU_HH__ 50 51#include <list> 52 53#include "base/hashmap.hh" 54#include "mem/cache/tags/base.hh" 55#include "mem/cache/blk.hh" 56#include "mem/packet.hh" 57#include "params/FALRU.hh" 58 59/** 60 * A fully associative cache block. 61 */ 62class FALRUBlk : public CacheBlk 63{ 64public: 65 /** The previous block in LRU order. */ 66 FALRUBlk *prev; 67 /** The next block in LRU order. */ 68 FALRUBlk *next; 69 /** Has this block been touched? */ 70 bool isTouched; 71 72 /** 73 * A bit mask of the sizes of cache that this block is resident in. 74 * Each bit represents a power of 2 in MB size cache. 75 * If bit 0 is set, this block is in a 1MB cache 76 * If bit 2 is set, this block is in a 4MB cache, etc. 77 * There is one bit for each cache smaller than the full size (default 78 * 16MB). 79 */ 80 int inCache; 81}; 82 83/** 84 * A fully associative LRU cache. Keeps statistics for accesses to a number of 85 * cache sizes at once. 86 */ 87class FALRU : public BaseTags 88{ 89 public: 90 /** Typedef the block type used in this class. */ 91 typedef FALRUBlk BlkType; 92 /** Typedef a list of pointers to the local block type. */ 93 typedef std::list<FALRUBlk*> BlkList; 94 95 protected: 96 /** Array of pointers to blocks at the cache size boundaries. */ 97 FALRUBlk **cacheBoundaries; 98 /** A mask for the FALRUBlk::inCache bits. */ 99 int cacheMask; 100 /** The number of different size caches being tracked. */ 101 unsigned numCaches; 102 103 /** The cache blocks. */ 104 FALRUBlk *blks; 105 106 /** The MRU block. */ 107 FALRUBlk *head; 108 /** The LRU block. */ 109 FALRUBlk *tail; 110 111 /** Hash table type mapping addresses to cache block pointers. */ 112 typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t; 113 /** Iterator into the address hash table. */ 114 typedef hash_t::const_iterator tagIterator; 115 116 /** The address hash table. */ 117 hash_t tagHash; 118 119 /** 120 * Find the cache block for the given address. 121 * @param addr The address to find. 122 * @return The cache block of the address, if any. 123 */ 124 FALRUBlk * hashLookup(Addr addr) const; 125 126 /** 127 * Move a cache block to the MRU position. 128 * @param blk The block to promote. 129 */ 130 void moveToHead(FALRUBlk *blk); 131 132 /** 133 * Check to make sure all the cache boundaries are still where they should 134 * be. Used for debugging. 135 * @return True if everything is correct. 136 */ 137 bool check(); 138 139 /** 140 * @defgroup FALRUStats Fully Associative LRU specific statistics 141 * The FA lru stack lets us track multiple cache sizes at once. These 142 * statistics track the hits and misses for different cache sizes. 143 * @{ 144 */ 145 146 /** Hits in each cache size >= 128K. */ 147 Stats::Vector hits; 148 /** Misses in each cache size >= 128K. */ 149 Stats::Vector misses; 150 /** Total number of accesses. */ 151 Stats::Scalar accesses; 152 153 /** 154 * @} 155 */ 156 157public: 158 159 typedef FALRUParams Params; 160 161 /** 162 * Construct and initialize this cache tagstore. 163 */ 164 FALRU(const Params *p); 165 ~FALRU(); 166 167 /** 168 * Register the stats for this object. 169 * @param name The name to prepend to the stats name. 170 */ 171 void regStats(); 172 173 /** 174 * Invalidate a cache block. 175 * @param blk The block to invalidate. 176 */ 177 void invalidate(BlkType *blk); 178 179 /** 180 * Access block and update replacement data. May not succeed, in which case 181 * NULL pointer is returned. This has all the implications of a cache 182 * access and should only be used as such. 183 * Returns the access latency and inCache flags as a side effect. 184 * @param addr The address to look for. 185 * @param is_secure True if the target memory space is secure. 186 * @param asid The address space ID. 187 * @param lat The latency of the access. 188 * @param inCache The FALRUBlk::inCache flags. 189 * @return Pointer to the cache block. 190 */ 191 FALRUBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 192 int context_src, int *inCache = 0); 193 194 /** 195 * Find the block in the cache, do not update the replacement data. 196 * @param addr The address to look for. 197 * @param is_secure True if the target memory space is secure. 198 * @param asid The address space ID. 199 * @return Pointer to the cache block. 200 */ 201 FALRUBlk* findBlock(Addr addr, bool is_secure) const; 202 203 /** 204 * Find a replacement block for the address provided. 205 * @param pkt The request to a find a replacement candidate for. 206 * @return The block to place the replacement in. 207 */ 208 FALRUBlk* findVictim(Addr addr); 209 210 void insertBlock(PacketPtr pkt, BlkType *blk); 211 212 /** |
213 * Return the block size of this cache. 214 * @return The block size. 215 */ 216 unsigned 217 getBlockSize() const 218 { 219 return blkSize; 220 } 221 222 /** 223 * Return the subblock size of this cache, always the block size. 224 * @return The block size. 225 */ 226 unsigned 227 getSubBlockSize() const 228 { 229 return blkSize; 230 } 231 232 /** 233 * Align an address to the block size. 234 * @param addr the address to align. 235 * @return The aligned address. 236 */ 237 Addr blkAlign(Addr addr) const 238 { 239 return (addr & ~(Addr)(blkSize-1)); 240 } 241 242 /** 243 * Generate the tag from the addres. For fully associative this is just the 244 * block address. 245 * @param addr The address to get the tag from. 246 * @return The tag. 247 */ 248 Addr extractTag(Addr addr) const 249 { 250 return blkAlign(addr); 251 } 252 253 /** 254 * Return the set of an address. Only one set in a fully associative cache. 255 * @param addr The address to get the set from. 256 * @return 0. 257 */ 258 int extractSet(Addr addr) const 259 { 260 return 0; 261 } 262 263 /** 264 * Calculate the block offset of an address. 265 * @param addr the address to get the offset of. 266 * @return the block offset. 267 */ 268 int extractBlkOffset(Addr addr) const 269 { 270 return (addr & (Addr)(blkSize-1)); 271 } 272 273 /** 274 * Regenerate the block address from the tag and the set. 275 * @param tag The tag of the block. 276 * @param set The set the block belongs to. 277 * @return the block address. 278 */ 279 Addr regenerateBlkAddr(Addr tag, int set) const 280 { 281 return (tag); 282 } 283 284 /** 285 *iterated through all blocks and clear all locks 286 *Needed to clear all lock tracking at once 287 */ 288 virtual void clearLocks(); 289 290 /** 291 * @todo Implement as in lru. Currently not used 292 */ 293 virtual std::string print() const { return ""; } 294 295 /** 296 * Visit each block in the tag store and apply a visitor to the 297 * block. 298 * 299 * The visitor should be a function (or object that behaves like a 300 * function) that takes a cache block reference as its parameter 301 * and returns a bool. A visitor can request the traversal to be 302 * stopped by returning false, returning true causes it to be 303 * called for the next block in the tag store. 304 * 305 * \param visitor Visitor to call on each block. 306 */ 307 template <typename V> 308 void forEachBlk(V &visitor) { 309 for (int i = 0; i < numBlocks; i++) { 310 if (!visitor(blks[i])) 311 return; 312 } 313 } 314 315}; 316 317#endif // __MEM_CACHE_TAGS_FA_LRU_HH__ |