1/* 2 * Copyright (c) 2012-2013,2016,2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 36 unchanged lines hidden (view full) --- 45 * @file 46 * Declaration of a fully associative LRU tag store. 47 */ 48 49#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ 50#define __MEM_CACHE_TAGS_FA_LRU_HH__ 51 52#include <cstdint> |
53#include <functional> |
54#include <string> 55#include <unordered_map> 56 57#include "base/bitfield.hh" 58#include "base/intmath.hh" 59#include "base/logging.hh" 60#include "base/statistics.hh" 61#include "base/types.hh" --- 174 unchanged lines hidden (view full) --- 236 * @param block The block. 237 * @return the block address. 238 */ 239 Addr regenerateBlkAddr(const CacheBlk* blk) const override 240 { 241 return blk->tag; 242 } 243 |
244 void forEachBlk(std::function<void(CacheBlk &)> visitor) override { 245 for (int i = 0; i < numBlocks; i++) { 246 visitor(blks[i]); 247 } 248 } |
249 |
250 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override { |
251 for (int i = 0; i < numBlocks; i++) { |
252 if (visitor(blks[i])) { 253 return true; 254 } |
255 } |
256 return false; |
257 } 258 259 private: 260 /** 261 * Mechanism that allows us to simultaneously collect miss 262 * statistics for multiple caches. Currently, we keep track of 263 * caches from a set minimum size of interest up to the actual 264 * cache size. --- 120 unchanged lines hidden --- |