1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a fully associative LRU tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
49#define __MEM_CACHE_TAGS_FA_LRU_HH__
50
51#include <list>
52
53#include "base/hashmap.hh"
54#include "mem/cache/tags/base.hh"
55#include "mem/cache/blk.hh"
56#include "mem/packet.hh"
57#include "params/FALRU.hh"
58
59/**
60 * A fully associative cache block.
61 */
62class FALRUBlk : public CacheBlk
63{
64public:
65 /** The previous block in LRU order. */
66 FALRUBlk *prev;
67 /** The next block in LRU order. */
68 FALRUBlk *next;
69 /** Has this block been touched? */
70 bool isTouched;
71
72 /**
73 * A bit mask of the sizes of cache that this block is resident in.
74 * Each bit represents a power of 2 in MB size cache.
75 * If bit 0 is set, this block is in a 1MB cache
76 * If bit 2 is set, this block is in a 4MB cache, etc.
77 * There is one bit for each cache smaller than the full size (default
78 * 16MB).
79 */
80 int inCache;
81};
82
83/**
84 * A fully associative LRU cache. Keeps statistics for accesses to a number of
85 * cache sizes at once.
86 */
87class FALRU : public BaseTags
88{
89 public:
90 /** Typedef the block type used in this class. */
91 typedef FALRUBlk BlkType;
92 /** Typedef a list of pointers to the local block type. */
93 typedef std::list<FALRUBlk*> BlkList;
94
95 protected:
96 /** Array of pointers to blocks at the cache size boundaries. */
97 FALRUBlk **cacheBoundaries;
98 /** A mask for the FALRUBlk::inCache bits. */
99 int cacheMask;
100 /** The number of different size caches being tracked. */
101 unsigned numCaches;
102
103 /** The cache blocks. */
104 FALRUBlk *blks;
105
106 /** The MRU block. */
107 FALRUBlk *head;
108 /** The LRU block. */
109 FALRUBlk *tail;
110
111 /** Hash table type mapping addresses to cache block pointers. */
112 typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t;
113 /** Iterator into the address hash table. */
114 typedef hash_t::const_iterator tagIterator;
115
116 /** The address hash table. */
117 hash_t tagHash;
118
119 /**
120 * Find the cache block for the given address.
121 * @param addr The address to find.
122 * @return The cache block of the address, if any.
123 */
124 FALRUBlk * hashLookup(Addr addr) const;
125
126 /**
127 * Move a cache block to the MRU position.
128 * @param blk The block to promote.
129 */
130 void moveToHead(FALRUBlk *blk);
131
132 /**
133 * Check to make sure all the cache boundaries are still where they should
134 * be. Used for debugging.
135 * @return True if everything is correct.
136 */
137 bool check();
138
139 /**
140 * @defgroup FALRUStats Fully Associative LRU specific statistics
141 * The FA lru stack lets us track multiple cache sizes at once. These
142 * statistics track the hits and misses for different cache sizes.
143 * @{
144 */
145
146 /** Hits in each cache size >= 128K. */
147 Stats::Vector hits;
148 /** Misses in each cache size >= 128K. */
149 Stats::Vector misses;
150 /** Total number of accesses. */
151 Stats::Scalar accesses;
152
153 /**
154 * @}
155 */
156
157public:
158
159 typedef FALRUParams Params;
160
161 /**
162 * Construct and initialize this cache tagstore.
163 */
164 FALRU(const Params *p);
165 ~FALRU();
166
167 /**
168 * Register the stats for this object.
169 * @param name The name to prepend to the stats name.
170 */
171 void regStats();
172
173 /**
174 * Invalidate a cache block.
175 * @param blk The block to invalidate.
176 */
177 void invalidate(BlkType *blk);
178
179 /**
180 * Access block and update replacement data. May not succeed, in which case
181 * NULL pointer is returned. This has all the implications of a cache
182 * access and should only be used as such.
183 * Returns the access latency and inCache flags as a side effect.
184 * @param addr The address to look for.
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a fully associative LRU tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
49#define __MEM_CACHE_TAGS_FA_LRU_HH__
50
51#include <list>
52
53#include "base/hashmap.hh"
54#include "mem/cache/tags/base.hh"
55#include "mem/cache/blk.hh"
56#include "mem/packet.hh"
57#include "params/FALRU.hh"
58
59/**
60 * A fully associative cache block.
61 */
62class FALRUBlk : public CacheBlk
63{
64public:
65 /** The previous block in LRU order. */
66 FALRUBlk *prev;
67 /** The next block in LRU order. */
68 FALRUBlk *next;
69 /** Has this block been touched? */
70 bool isTouched;
71
72 /**
73 * A bit mask of the sizes of cache that this block is resident in.
74 * Each bit represents a power of 2 in MB size cache.
75 * If bit 0 is set, this block is in a 1MB cache
76 * If bit 2 is set, this block is in a 4MB cache, etc.
77 * There is one bit for each cache smaller than the full size (default
78 * 16MB).
79 */
80 int inCache;
81};
82
83/**
84 * A fully associative LRU cache. Keeps statistics for accesses to a number of
85 * cache sizes at once.
86 */
87class FALRU : public BaseTags
88{
89 public:
90 /** Typedef the block type used in this class. */
91 typedef FALRUBlk BlkType;
92 /** Typedef a list of pointers to the local block type. */
93 typedef std::list<FALRUBlk*> BlkList;
94
95 protected:
96 /** Array of pointers to blocks at the cache size boundaries. */
97 FALRUBlk **cacheBoundaries;
98 /** A mask for the FALRUBlk::inCache bits. */
99 int cacheMask;
100 /** The number of different size caches being tracked. */
101 unsigned numCaches;
102
103 /** The cache blocks. */
104 FALRUBlk *blks;
105
106 /** The MRU block. */
107 FALRUBlk *head;
108 /** The LRU block. */
109 FALRUBlk *tail;
110
111 /** Hash table type mapping addresses to cache block pointers. */
112 typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t;
113 /** Iterator into the address hash table. */
114 typedef hash_t::const_iterator tagIterator;
115
116 /** The address hash table. */
117 hash_t tagHash;
118
119 /**
120 * Find the cache block for the given address.
121 * @param addr The address to find.
122 * @return The cache block of the address, if any.
123 */
124 FALRUBlk * hashLookup(Addr addr) const;
125
126 /**
127 * Move a cache block to the MRU position.
128 * @param blk The block to promote.
129 */
130 void moveToHead(FALRUBlk *blk);
131
132 /**
133 * Check to make sure all the cache boundaries are still where they should
134 * be. Used for debugging.
135 * @return True if everything is correct.
136 */
137 bool check();
138
139 /**
140 * @defgroup FALRUStats Fully Associative LRU specific statistics
141 * The FA lru stack lets us track multiple cache sizes at once. These
142 * statistics track the hits and misses for different cache sizes.
143 * @{
144 */
145
146 /** Hits in each cache size >= 128K. */
147 Stats::Vector hits;
148 /** Misses in each cache size >= 128K. */
149 Stats::Vector misses;
150 /** Total number of accesses. */
151 Stats::Scalar accesses;
152
153 /**
154 * @}
155 */
156
157public:
158
159 typedef FALRUParams Params;
160
161 /**
162 * Construct and initialize this cache tagstore.
163 */
164 FALRU(const Params *p);
165 ~FALRU();
166
167 /**
168 * Register the stats for this object.
169 * @param name The name to prepend to the stats name.
170 */
171 void regStats();
172
173 /**
174 * Invalidate a cache block.
175 * @param blk The block to invalidate.
176 */
177 void invalidate(BlkType *blk);
178
179 /**
180 * Access block and update replacement data. May not succeed, in which case
181 * NULL pointer is returned. This has all the implications of a cache
182 * access and should only be used as such.
183 * Returns the access latency and inCache flags as a side effect.
184 * @param addr The address to look for.
|
199
200 /**
201 * Find a replacement block for the address provided.
202 * @param pkt The request to a find a replacement candidate for.
203 * @param writebacks List for any writebacks to be performed.
204 * @return The block to place the replacement in.
205 */
206 FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
207
208 void insertBlock(PacketPtr pkt, BlkType *blk);
209
210 /**
211 * Return the hit latency of this cache.
212 * @return The hit latency.
213 */
214 Cycles getHitLatency() const
215 {
216 return hitLatency;
217 }
218
219 /**
220 * Return the block size of this cache.
221 * @return The block size.
222 */
223 unsigned
224 getBlockSize() const
225 {
226 return blkSize;
227 }
228
229 /**
230 * Return the subblock size of this cache, always the block size.
231 * @return The block size.
232 */
233 unsigned
234 getSubBlockSize() const
235 {
236 return blkSize;
237 }
238
239 /**
240 * Align an address to the block size.
241 * @param addr the address to align.
242 * @return The aligned address.
243 */
244 Addr blkAlign(Addr addr) const
245 {
246 return (addr & ~(Addr)(blkSize-1));
247 }
248
249 /**
250 * Generate the tag from the addres. For fully associative this is just the
251 * block address.
252 * @param addr The address to get the tag from.
253 * @return The tag.
254 */
255 Addr extractTag(Addr addr) const
256 {
257 return blkAlign(addr);
258 }
259
260 /**
261 * Return the set of an address. Only one set in a fully associative cache.
262 * @param addr The address to get the set from.
263 * @return 0.
264 */
265 int extractSet(Addr addr) const
266 {
267 return 0;
268 }
269
270 /**
271 * Calculate the block offset of an address.
272 * @param addr the address to get the offset of.
273 * @return the block offset.
274 */
275 int extractBlkOffset(Addr addr) const
276 {
277 return (addr & (Addr)(blkSize-1));
278 }
279
280 /**
281 * Regenerate the block address from the tag and the set.
282 * @param tag The tag of the block.
283 * @param set The set the block belongs to.
284 * @return the block address.
285 */
286 Addr regenerateBlkAddr(Addr tag, int set) const
287 {
288 return (tag);
289 }
290
291 /**
292 *iterated through all blocks and clear all locks
293 *Needed to clear all lock tracking at once
294 */
295 virtual void clearLocks();
296
297 /**
298 * @todo Implement as in lru. Currently not used
299 */
300 virtual std::string print() const { return ""; }
301
302 /**
303 * Visit each block in the tag store and apply a visitor to the
304 * block.
305 *
306 * The visitor should be a function (or object that behaves like a
307 * function) that takes a cache block reference as its parameter
308 * and returns a bool. A visitor can request the traversal to be
309 * stopped by returning false, returning true causes it to be
310 * called for the next block in the tag store.
311 *
312 * \param visitor Visitor to call on each block.
313 */
314 template <typename V>
315 void forEachBlk(V &visitor) {
316 for (int i = 0; i < numBlocks; i++) {
317 if (!visitor(blks[i]))
318 return;
319 }
320 }
321
322};
323
324#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
| 202
203 /**
204 * Find a replacement block for the address provided.
205 * @param pkt The request to a find a replacement candidate for.
206 * @param writebacks List for any writebacks to be performed.
207 * @return The block to place the replacement in.
208 */
209 FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
210
211 void insertBlock(PacketPtr pkt, BlkType *blk);
212
213 /**
214 * Return the hit latency of this cache.
215 * @return The hit latency.
216 */
217 Cycles getHitLatency() const
218 {
219 return hitLatency;
220 }
221
222 /**
223 * Return the block size of this cache.
224 * @return The block size.
225 */
226 unsigned
227 getBlockSize() const
228 {
229 return blkSize;
230 }
231
232 /**
233 * Return the subblock size of this cache, always the block size.
234 * @return The block size.
235 */
236 unsigned
237 getSubBlockSize() const
238 {
239 return blkSize;
240 }
241
242 /**
243 * Align an address to the block size.
244 * @param addr the address to align.
245 * @return The aligned address.
246 */
247 Addr blkAlign(Addr addr) const
248 {
249 return (addr & ~(Addr)(blkSize-1));
250 }
251
252 /**
253 * Generate the tag from the addres. For fully associative this is just the
254 * block address.
255 * @param addr The address to get the tag from.
256 * @return The tag.
257 */
258 Addr extractTag(Addr addr) const
259 {
260 return blkAlign(addr);
261 }
262
263 /**
264 * Return the set of an address. Only one set in a fully associative cache.
265 * @param addr The address to get the set from.
266 * @return 0.
267 */
268 int extractSet(Addr addr) const
269 {
270 return 0;
271 }
272
273 /**
274 * Calculate the block offset of an address.
275 * @param addr the address to get the offset of.
276 * @return the block offset.
277 */
278 int extractBlkOffset(Addr addr) const
279 {
280 return (addr & (Addr)(blkSize-1));
281 }
282
283 /**
284 * Regenerate the block address from the tag and the set.
285 * @param tag The tag of the block.
286 * @param set The set the block belongs to.
287 * @return the block address.
288 */
289 Addr regenerateBlkAddr(Addr tag, int set) const
290 {
291 return (tag);
292 }
293
294 /**
295 *iterated through all blocks and clear all locks
296 *Needed to clear all lock tracking at once
297 */
298 virtual void clearLocks();
299
300 /**
301 * @todo Implement as in lru. Currently not used
302 */
303 virtual std::string print() const { return ""; }
304
305 /**
306 * Visit each block in the tag store and apply a visitor to the
307 * block.
308 *
309 * The visitor should be a function (or object that behaves like a
310 * function) that takes a cache block reference as its parameter
311 * and returns a bool. A visitor can request the traversal to be
312 * stopped by returning false, returning true causes it to be
313 * called for the next block in the tag store.
314 *
315 * \param visitor Visitor to call on each block.
316 */
317 template <typename V>
318 void forEachBlk(V &visitor) {
319 for (int i = 0; i < numBlocks; i++) {
320 if (!visitor(blks[i]))
321 return;
322 }
323 }
324
325};
326
327#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
|