1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a fully associative LRU tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
49#define __MEM_CACHE_TAGS_FA_LRU_HH__
50
51#include <list>
52
53#include "base/hashmap.hh"
54#include "mem/cache/tags/base.hh"
55#include "mem/cache/blk.hh"
56#include "mem/packet.hh"
57
58/**
59 * A fully associative cache block.
60 */
61class FALRUBlk : public CacheBlk
62{
63public:
64 /** The previous block in LRU order. */
65 FALRUBlk *prev;
66 /** The next block in LRU order. */
67 FALRUBlk *next;
68 /** Has this block been touched? */
69 bool isTouched;
70
71 /**
72 * A bit mask of the sizes of cache that this block is resident in.
73 * Each bit represents a power of 2 in MB size cache.
74 * If bit 0 is set, this block is in a 1MB cache
75 * If bit 2 is set, this block is in a 4MB cache, etc.
76 * There is one bit for each cache smaller than the full size (default
77 * 16MB).
78 */
79 int inCache;
80};
81
82/**
83 * A fully associative LRU cache. Keeps statistics for accesses to a number of
84 * cache sizes at once.
85 */
86class FALRU : public BaseTags
87{
88 public:
89 /** Typedef the block type used in this class. */
90 typedef FALRUBlk BlkType;
91 /** Typedef a list of pointers to the local block type. */
92 typedef std::list<FALRUBlk*> BlkList;
93
94 protected:
95 /** The block size of the cache. */
96 const unsigned blkSize;
97 /** The size of the cache. */
98 const unsigned size;
99 /** The hit latency of the cache. */
100 const Cycles hitLatency;
101
102 /** Array of pointers to blocks at the cache size boundaries. */
103 FALRUBlk **cacheBoundaries;
104 /** A mask for the FALRUBlk::inCache bits. */
105 int cacheMask;
106 /** The number of different size caches being tracked. */
107 unsigned numCaches;
108
109 /** The cache blocks. */
110 FALRUBlk *blks;
111
112 /** The MRU block. */
113 FALRUBlk *head;
114 /** The LRU block. */
115 FALRUBlk *tail;
116
117 /** Hash table type mapping addresses to cache block pointers. */
118 typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t;
119 /** Iterator into the address hash table. */
120 typedef hash_t::const_iterator tagIterator;
121
122 /** The address hash table. */
123 hash_t tagHash;
124
125 /**
126 * Find the cache block for the given address.
127 * @param addr The address to find.
128 * @return The cache block of the address, if any.
129 */
130 FALRUBlk * hashLookup(Addr addr) const;
131
132 /**
133 * Move a cache block to the MRU position.
134 * @param blk The block to promote.
135 */
136 void moveToHead(FALRUBlk *blk);
137
138 /**
139 * Check to make sure all the cache boundaries are still where they should
140 * be. Used for debugging.
141 * @return True if everything is correct.
142 */
143 bool check();
144
145 /**
146 * @defgroup FALRUStats Fully Associative LRU specific statistics
147 * The FA lru stack lets us track multiple cache sizes at once. These
148 * statistics track the hits and misses for different cache sizes.
149 * @{
150 */
151
152 /** Hits in each cache size >= 128K. */
153 Stats::Vector hits;
154 /** Misses in each cache size >= 128K. */
155 Stats::Vector misses;
156 /** Total number of accesses. */
157 Stats::Scalar accesses;
158
159 /**
160 * @}
161 */
162
163public:
164 /**
165 * Construct and initialize this cache tagstore.
166 * @param blkSize The block size of the cache.
167 * @param size The size of the cache.
168 * @param hit_latency The hit latency of the cache.
169 */
170 FALRU(unsigned blkSize, unsigned size, Cycles hit_latency);
171 ~FALRU();
172
173 /**
174 * Register the stats for this object.
175 * @param name The name to prepend to the stats name.
176 */
177 void regStats(const std::string &name);
178
179 /**
180 * Invalidate a cache block.
181 * @param blk The block to invalidate.
182 */
183 void invalidate(BlkType *blk);
184
185 /**
186 * Access block and update replacement data. May not succeed, in which case
187 * NULL pointer is returned. This has all the implications of a cache
188 * access and should only be used as such.
189 * Returns the access latency and inCache flags as a side effect.
190 * @param addr The address to look for.
191 * @param asid The address space ID.
192 * @param lat The latency of the access.
193 * @param inCache The FALRUBlk::inCache flags.
194 * @return Pointer to the cache block.
195 */
196 FALRUBlk* accessBlock(Addr addr, Cycles &lat, int context_src, int *inCache = 0);
197
198 /**
199 * Find the block in the cache, do not update the replacement data.
200 * @param addr The address to look for.
201 * @param asid The address space ID.
202 * @return Pointer to the cache block.
203 */
204 FALRUBlk* findBlock(Addr addr) const;
205
206 /**
207 * Find a replacement block for the address provided.
208 * @param pkt The request to a find a replacement candidate for.
209 * @param writebacks List for any writebacks to be performed.
210 * @return The block to place the replacement in.
211 */
212 FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
213
214 void insertBlock(Addr addr, BlkType *blk, int context_src);
215
216 /**
217 * Return the hit latency of this cache.
218 * @return The hit latency.
219 */
220 Cycles getHitLatency() const
221 {
222 return hitLatency;
223 }
224
225 /**
226 * Return the block size of this cache.
227 * @return The block size.
228 */
229 unsigned
230 getBlockSize() const
231 {
232 return blkSize;
233 }
234
235 /**
236 * Return the subblock size of this cache, always the block size.
237 * @return The block size.
238 */
239 unsigned
240 getSubBlockSize() const
241 {
242 return blkSize;
243 }
244
245 /**
246 * Align an address to the block size.
247 * @param addr the address to align.
248 * @return The aligned address.
249 */
250 Addr blkAlign(Addr addr) const
251 {
252 return (addr & ~(Addr)(blkSize-1));
253 }
254
255 /**
256 * Generate the tag from the addres. For fully associative this is just the
257 * block address.
258 * @param addr The address to get the tag from.
259 * @return The tag.
260 */
261 Addr extractTag(Addr addr) const
262 {
263 return blkAlign(addr);
264 }
265
266 /**
267 * Return the set of an address. Only one set in a fully associative cache.
268 * @param addr The address to get the set from.
269 * @return 0.
270 */
271 int extractSet(Addr addr) const
272 {
273 return 0;
274 }
275
276 /**
277 * Calculate the block offset of an address.
278 * @param addr the address to get the offset of.
279 * @return the block offset.
280 */
281 int extractBlkOffset(Addr addr) const
282 {
283 return (addr & (Addr)(blkSize-1));
284 }
285
286 /**
287 * Regenerate the block address from the tag and the set.
288 * @param tag The tag of the block.
289 * @param set The set the block belongs to.
290 * @return the block address.
291 */
292 Addr regenerateBlkAddr(Addr tag, int set) const
293 {
294 return (tag);
295 }
296
297 /**
298 *iterated through all blocks and clear all locks
299 *Needed to clear all lock tracking at once
300 */
301 virtual void clearLocks();
302
303 /**
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a fully associative LRU tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
49#define __MEM_CACHE_TAGS_FA_LRU_HH__
50
51#include <list>
52
53#include "base/hashmap.hh"
54#include "mem/cache/tags/base.hh"
55#include "mem/cache/blk.hh"
56#include "mem/packet.hh"
57
58/**
59 * A fully associative cache block.
60 */
61class FALRUBlk : public CacheBlk
62{
63public:
64 /** The previous block in LRU order. */
65 FALRUBlk *prev;
66 /** The next block in LRU order. */
67 FALRUBlk *next;
68 /** Has this block been touched? */
69 bool isTouched;
70
71 /**
72 * A bit mask of the sizes of cache that this block is resident in.
73 * Each bit represents a power of 2 in MB size cache.
74 * If bit 0 is set, this block is in a 1MB cache
75 * If bit 2 is set, this block is in a 4MB cache, etc.
76 * There is one bit for each cache smaller than the full size (default
77 * 16MB).
78 */
79 int inCache;
80};
81
82/**
83 * A fully associative LRU cache. Keeps statistics for accesses to a number of
84 * cache sizes at once.
85 */
86class FALRU : public BaseTags
87{
88 public:
89 /** Typedef the block type used in this class. */
90 typedef FALRUBlk BlkType;
91 /** Typedef a list of pointers to the local block type. */
92 typedef std::list<FALRUBlk*> BlkList;
93
94 protected:
95 /** The block size of the cache. */
96 const unsigned blkSize;
97 /** The size of the cache. */
98 const unsigned size;
99 /** The hit latency of the cache. */
100 const Cycles hitLatency;
101
102 /** Array of pointers to blocks at the cache size boundaries. */
103 FALRUBlk **cacheBoundaries;
104 /** A mask for the FALRUBlk::inCache bits. */
105 int cacheMask;
106 /** The number of different size caches being tracked. */
107 unsigned numCaches;
108
109 /** The cache blocks. */
110 FALRUBlk *blks;
111
112 /** The MRU block. */
113 FALRUBlk *head;
114 /** The LRU block. */
115 FALRUBlk *tail;
116
117 /** Hash table type mapping addresses to cache block pointers. */
118 typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t;
119 /** Iterator into the address hash table. */
120 typedef hash_t::const_iterator tagIterator;
121
122 /** The address hash table. */
123 hash_t tagHash;
124
125 /**
126 * Find the cache block for the given address.
127 * @param addr The address to find.
128 * @return The cache block of the address, if any.
129 */
130 FALRUBlk * hashLookup(Addr addr) const;
131
132 /**
133 * Move a cache block to the MRU position.
134 * @param blk The block to promote.
135 */
136 void moveToHead(FALRUBlk *blk);
137
138 /**
139 * Check to make sure all the cache boundaries are still where they should
140 * be. Used for debugging.
141 * @return True if everything is correct.
142 */
143 bool check();
144
145 /**
146 * @defgroup FALRUStats Fully Associative LRU specific statistics
147 * The FA lru stack lets us track multiple cache sizes at once. These
148 * statistics track the hits and misses for different cache sizes.
149 * @{
150 */
151
152 /** Hits in each cache size >= 128K. */
153 Stats::Vector hits;
154 /** Misses in each cache size >= 128K. */
155 Stats::Vector misses;
156 /** Total number of accesses. */
157 Stats::Scalar accesses;
158
159 /**
160 * @}
161 */
162
163public:
164 /**
165 * Construct and initialize this cache tagstore.
166 * @param blkSize The block size of the cache.
167 * @param size The size of the cache.
168 * @param hit_latency The hit latency of the cache.
169 */
170 FALRU(unsigned blkSize, unsigned size, Cycles hit_latency);
171 ~FALRU();
172
173 /**
174 * Register the stats for this object.
175 * @param name The name to prepend to the stats name.
176 */
177 void regStats(const std::string &name);
178
179 /**
180 * Invalidate a cache block.
181 * @param blk The block to invalidate.
182 */
183 void invalidate(BlkType *blk);
184
185 /**
186 * Access block and update replacement data. May not succeed, in which case
187 * NULL pointer is returned. This has all the implications of a cache
188 * access and should only be used as such.
189 * Returns the access latency and inCache flags as a side effect.
190 * @param addr The address to look for.
191 * @param asid The address space ID.
192 * @param lat The latency of the access.
193 * @param inCache The FALRUBlk::inCache flags.
194 * @return Pointer to the cache block.
195 */
196 FALRUBlk* accessBlock(Addr addr, Cycles &lat, int context_src, int *inCache = 0);
197
198 /**
199 * Find the block in the cache, do not update the replacement data.
200 * @param addr The address to look for.
201 * @param asid The address space ID.
202 * @return Pointer to the cache block.
203 */
204 FALRUBlk* findBlock(Addr addr) const;
205
206 /**
207 * Find a replacement block for the address provided.
208 * @param pkt The request to a find a replacement candidate for.
209 * @param writebacks List for any writebacks to be performed.
210 * @return The block to place the replacement in.
211 */
212 FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
213
214 void insertBlock(Addr addr, BlkType *blk, int context_src);
215
216 /**
217 * Return the hit latency of this cache.
218 * @return The hit latency.
219 */
220 Cycles getHitLatency() const
221 {
222 return hitLatency;
223 }
224
225 /**
226 * Return the block size of this cache.
227 * @return The block size.
228 */
229 unsigned
230 getBlockSize() const
231 {
232 return blkSize;
233 }
234
235 /**
236 * Return the subblock size of this cache, always the block size.
237 * @return The block size.
238 */
239 unsigned
240 getSubBlockSize() const
241 {
242 return blkSize;
243 }
244
245 /**
246 * Align an address to the block size.
247 * @param addr the address to align.
248 * @return The aligned address.
249 */
250 Addr blkAlign(Addr addr) const
251 {
252 return (addr & ~(Addr)(blkSize-1));
253 }
254
255 /**
256 * Generate the tag from the addres. For fully associative this is just the
257 * block address.
258 * @param addr The address to get the tag from.
259 * @return The tag.
260 */
261 Addr extractTag(Addr addr) const
262 {
263 return blkAlign(addr);
264 }
265
266 /**
267 * Return the set of an address. Only one set in a fully associative cache.
268 * @param addr The address to get the set from.
269 * @return 0.
270 */
271 int extractSet(Addr addr) const
272 {
273 return 0;
274 }
275
276 /**
277 * Calculate the block offset of an address.
278 * @param addr the address to get the offset of.
279 * @return the block offset.
280 */
281 int extractBlkOffset(Addr addr) const
282 {
283 return (addr & (Addr)(blkSize-1));
284 }
285
286 /**
287 * Regenerate the block address from the tag and the set.
288 * @param tag The tag of the block.
289 * @param set The set the block belongs to.
290 * @return the block address.
291 */
292 Addr regenerateBlkAddr(Addr tag, int set) const
293 {
294 return (tag);
295 }
296
297 /**
298 *iterated through all blocks and clear all locks
299 *Needed to clear all lock tracking at once
300 */
301 virtual void clearLocks();
302
303 /**
|