1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31/**
32 * @file
33 * Declaration of a fully associative LRU tag store.
34 */
35
36#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
37#define __MEM_CACHE_TAGS_FA_LRU_HH__
38
39#include <list>
40
41#include "base/hashmap.hh"
42#include "mem/cache/tags/base.hh"
43#include "mem/cache/blk.hh"
44#include "mem/packet.hh"
45
46/**
47 * A fully associative cache block.
48 */
49class FALRUBlk : public CacheBlk
50{
51public:
52 /** The previous block in LRU order. */
53 FALRUBlk *prev;
54 /** The next block in LRU order. */
55 FALRUBlk *next;
56 /** Has this block been touched? */
57 bool isTouched;
58
59 /**
60 * A bit mask of the sizes of cache that this block is resident in.
61 * Each bit represents a power of 2 in MB size cache.
62 * If bit 0 is set, this block is in a 1MB cache
63 * If bit 2 is set, this block is in a 4MB cache, etc.
64 * There is one bit for each cache smaller than the full size (default
65 * 16MB).
66 */
67 int inCache;
68};
69
70/**
71 * A fully associative LRU cache. Keeps statistics for accesses to a number of
72 * cache sizes at once.
73 */
74class FALRU : public BaseTags
75{
76 public:
77 /** Typedef the block type used in this class. */
78 typedef FALRUBlk BlkType;
79 /** Typedef a list of pointers to the local block type. */
80 typedef std::list<FALRUBlk*> BlkList;
81
82 protected:
83 /** The block size of the cache. */
84 const unsigned blkSize;
85 /** The size of the cache. */
86 const unsigned size;
87 /** The hit latency of the cache. */
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31/**
32 * @file
33 * Declaration of a fully associative LRU tag store.
34 */
35
36#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
37#define __MEM_CACHE_TAGS_FA_LRU_HH__
38
39#include <list>
40
41#include "base/hashmap.hh"
42#include "mem/cache/tags/base.hh"
43#include "mem/cache/blk.hh"
44#include "mem/packet.hh"
45
46/**
47 * A fully associative cache block.
48 */
49class FALRUBlk : public CacheBlk
50{
51public:
52 /** The previous block in LRU order. */
53 FALRUBlk *prev;
54 /** The next block in LRU order. */
55 FALRUBlk *next;
56 /** Has this block been touched? */
57 bool isTouched;
58
59 /**
60 * A bit mask of the sizes of cache that this block is resident in.
61 * Each bit represents a power of 2 in MB size cache.
62 * If bit 0 is set, this block is in a 1MB cache
63 * If bit 2 is set, this block is in a 4MB cache, etc.
64 * There is one bit for each cache smaller than the full size (default
65 * 16MB).
66 */
67 int inCache;
68};
69
70/**
71 * A fully associative LRU cache. Keeps statistics for accesses to a number of
72 * cache sizes at once.
73 */
74class FALRU : public BaseTags
75{
76 public:
77 /** Typedef the block type used in this class. */
78 typedef FALRUBlk BlkType;
79 /** Typedef a list of pointers to the local block type. */
80 typedef std::list<FALRUBlk*> BlkList;
81
82 protected:
83 /** The block size of the cache. */
84 const unsigned blkSize;
85 /** The size of the cache. */
86 const unsigned size;
87 /** The hit latency of the cache. */
|
88 const unsigned hitLatency;
| 88 const Cycles hitLatency;
|
89
90 /** Array of pointers to blocks at the cache size boundaries. */
91 FALRUBlk **cacheBoundaries;
92 /** A mask for the FALRUBlk::inCache bits. */
93 int cacheMask;
94 /** The number of different size caches being tracked. */
95 unsigned numCaches;
96
97 /** The cache blocks. */
98 FALRUBlk *blks;
99
100 /** The MRU block. */
101 FALRUBlk *head;
102 /** The LRU block. */
103 FALRUBlk *tail;
104
105 /** Hash table type mapping addresses to cache block pointers. */
106 typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t;
107 /** Iterator into the address hash table. */
108 typedef hash_t::const_iterator tagIterator;
109
110 /** The address hash table. */
111 hash_t tagHash;
112
113 /**
114 * Find the cache block for the given address.
115 * @param addr The address to find.
116 * @return The cache block of the address, if any.
117 */
118 FALRUBlk * hashLookup(Addr addr) const;
119
120 /**
121 * Move a cache block to the MRU position.
122 * @param blk The block to promote.
123 */
124 void moveToHead(FALRUBlk *blk);
125
126 /**
127 * Check to make sure all the cache boundaries are still where they should
128 * be. Used for debugging.
129 * @return True if everything is correct.
130 */
131 bool check();
132
133 /**
134 * @defgroup FALRUStats Fully Associative LRU specific statistics
135 * The FA lru stack lets us track multiple cache sizes at once. These
136 * statistics track the hits and misses for different cache sizes.
137 * @{
138 */
139
140 /** Hits in each cache size >= 128K. */
141 Stats::Vector hits;
142 /** Misses in each cache size >= 128K. */
143 Stats::Vector misses;
144 /** Total number of accesses. */
145 Stats::Scalar accesses;
146
147 /**
148 * @}
149 */
150
151public:
152 /**
153 * Construct and initialize this cache tagstore.
154 * @param blkSize The block size of the cache.
155 * @param size The size of the cache.
156 * @param hit_latency The hit latency of the cache.
157 */
| 89
90 /** Array of pointers to blocks at the cache size boundaries. */
91 FALRUBlk **cacheBoundaries;
92 /** A mask for the FALRUBlk::inCache bits. */
93 int cacheMask;
94 /** The number of different size caches being tracked. */
95 unsigned numCaches;
96
97 /** The cache blocks. */
98 FALRUBlk *blks;
99
100 /** The MRU block. */
101 FALRUBlk *head;
102 /** The LRU block. */
103 FALRUBlk *tail;
104
105 /** Hash table type mapping addresses to cache block pointers. */
106 typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t;
107 /** Iterator into the address hash table. */
108 typedef hash_t::const_iterator tagIterator;
109
110 /** The address hash table. */
111 hash_t tagHash;
112
113 /**
114 * Find the cache block for the given address.
115 * @param addr The address to find.
116 * @return The cache block of the address, if any.
117 */
118 FALRUBlk * hashLookup(Addr addr) const;
119
120 /**
121 * Move a cache block to the MRU position.
122 * @param blk The block to promote.
123 */
124 void moveToHead(FALRUBlk *blk);
125
126 /**
127 * Check to make sure all the cache boundaries are still where they should
128 * be. Used for debugging.
129 * @return True if everything is correct.
130 */
131 bool check();
132
133 /**
134 * @defgroup FALRUStats Fully Associative LRU specific statistics
135 * The FA lru stack lets us track multiple cache sizes at once. These
136 * statistics track the hits and misses for different cache sizes.
137 * @{
138 */
139
140 /** Hits in each cache size >= 128K. */
141 Stats::Vector hits;
142 /** Misses in each cache size >= 128K. */
143 Stats::Vector misses;
144 /** Total number of accesses. */
145 Stats::Scalar accesses;
146
147 /**
148 * @}
149 */
150
151public:
152 /**
153 * Construct and initialize this cache tagstore.
154 * @param blkSize The block size of the cache.
155 * @param size The size of the cache.
156 * @param hit_latency The hit latency of the cache.
157 */
|
158 FALRU(unsigned blkSize, unsigned size, unsigned hit_latency);
| 158 FALRU(unsigned blkSize, unsigned size, Cycles hit_latency);
|
159 ~FALRU();
160
161 /**
162 * Register the stats for this object.
163 * @param name The name to prepend to the stats name.
164 */
165 void regStats(const std::string &name);
166
167 /**
168 * Invalidate a cache block.
169 * @param blk The block to invalidate.
170 */
171 void invalidate(BlkType *blk);
172
173 /**
174 * Access block and update replacement data. May not succeed, in which case
175 * NULL pointer is returned. This has all the implications of a cache
176 * access and should only be used as such.
177 * Returns the access latency and inCache flags as a side effect.
178 * @param addr The address to look for.
179 * @param asid The address space ID.
180 * @param lat The latency of the access.
181 * @param inCache The FALRUBlk::inCache flags.
182 * @return Pointer to the cache block.
183 */
| 159 ~FALRU();
160
161 /**
162 * Register the stats for this object.
163 * @param name The name to prepend to the stats name.
164 */
165 void regStats(const std::string &name);
166
167 /**
168 * Invalidate a cache block.
169 * @param blk The block to invalidate.
170 */
171 void invalidate(BlkType *blk);
172
173 /**
174 * Access block and update replacement data. May not succeed, in which case
175 * NULL pointer is returned. This has all the implications of a cache
176 * access and should only be used as such.
177 * Returns the access latency and inCache flags as a side effect.
178 * @param addr The address to look for.
179 * @param asid The address space ID.
180 * @param lat The latency of the access.
181 * @param inCache The FALRUBlk::inCache flags.
182 * @return Pointer to the cache block.
183 */
|
184 FALRUBlk* accessBlock(Addr addr, int &lat, int context_src, int *inCache = 0);
| 184 FALRUBlk* accessBlock(Addr addr, Cycles &lat, int context_src, int *inCache = 0);
|
185
186 /**
187 * Find the block in the cache, do not update the replacement data.
188 * @param addr The address to look for.
189 * @param asid The address space ID.
190 * @return Pointer to the cache block.
191 */
192 FALRUBlk* findBlock(Addr addr) const;
193
194 /**
195 * Find a replacement block for the address provided.
196 * @param pkt The request to a find a replacement candidate for.
197 * @param writebacks List for any writebacks to be performed.
198 * @return The block to place the replacement in.
199 */
200 FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
201
202 void insertBlock(Addr addr, BlkType *blk, int context_src);
203
204 /**
205 * Return the hit latency of this cache.
206 * @return The hit latency.
207 */
| 185
186 /**
187 * Find the block in the cache, do not update the replacement data.
188 * @param addr The address to look for.
189 * @param asid The address space ID.
190 * @return Pointer to the cache block.
191 */
192 FALRUBlk* findBlock(Addr addr) const;
193
194 /**
195 * Find a replacement block for the address provided.
196 * @param pkt The request to a find a replacement candidate for.
197 * @param writebacks List for any writebacks to be performed.
198 * @return The block to place the replacement in.
199 */
200 FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
201
202 void insertBlock(Addr addr, BlkType *blk, int context_src);
203
204 /**
205 * Return the hit latency of this cache.
206 * @return The hit latency.
207 */
|
208 int getHitLatency() const
| 208 Cycles getHitLatency() const
|
209 {
210 return hitLatency;
211 }
212
213 /**
214 * Return the block size of this cache.
215 * @return The block size.
216 */
217 unsigned
218 getBlockSize() const
219 {
220 return blkSize;
221 }
222
223 /**
224 * Return the subblock size of this cache, always the block size.
225 * @return The block size.
226 */
227 unsigned
228 getSubBlockSize() const
229 {
230 return blkSize;
231 }
232
233 /**
234 * Align an address to the block size.
235 * @param addr the address to align.
236 * @return The aligned address.
237 */
238 Addr blkAlign(Addr addr) const
239 {
240 return (addr & ~(Addr)(blkSize-1));
241 }
242
243 /**
244 * Generate the tag from the addres. For fully associative this is just the
245 * block address.
246 * @param addr The address to get the tag from.
247 * @return The tag.
248 */
249 Addr extractTag(Addr addr) const
250 {
251 return blkAlign(addr);
252 }
253
254 /**
255 * Return the set of an address. Only one set in a fully associative cache.
256 * @param addr The address to get the set from.
257 * @return 0.
258 */
259 int extractSet(Addr addr) const
260 {
261 return 0;
262 }
263
264 /**
265 * Calculate the block offset of an address.
266 * @param addr the address to get the offset of.
267 * @return the block offset.
268 */
269 int extractBlkOffset(Addr addr) const
270 {
271 return (addr & (Addr)(blkSize-1));
272 }
273
274 /**
275 * Regenerate the block address from the tag and the set.
276 * @param tag The tag of the block.
277 * @param set The set the block belongs to.
278 * @return the block address.
279 */
280 Addr regenerateBlkAddr(Addr tag, int set) const
281 {
282 return (tag);
283 }
284
285 /**
286 *iterated through all blocks and clear all locks
287 *Needed to clear all lock tracking at once
288 */
289 virtual void clearLocks();
290};
291
292#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
| 209 {
210 return hitLatency;
211 }
212
213 /**
214 * Return the block size of this cache.
215 * @return The block size.
216 */
217 unsigned
218 getBlockSize() const
219 {
220 return blkSize;
221 }
222
223 /**
224 * Return the subblock size of this cache, always the block size.
225 * @return The block size.
226 */
227 unsigned
228 getSubBlockSize() const
229 {
230 return blkSize;
231 }
232
233 /**
234 * Align an address to the block size.
235 * @param addr the address to align.
236 * @return The aligned address.
237 */
238 Addr blkAlign(Addr addr) const
239 {
240 return (addr & ~(Addr)(blkSize-1));
241 }
242
243 /**
244 * Generate the tag from the addres. For fully associative this is just the
245 * block address.
246 * @param addr The address to get the tag from.
247 * @return The tag.
248 */
249 Addr extractTag(Addr addr) const
250 {
251 return blkAlign(addr);
252 }
253
254 /**
255 * Return the set of an address. Only one set in a fully associative cache.
256 * @param addr The address to get the set from.
257 * @return 0.
258 */
259 int extractSet(Addr addr) const
260 {
261 return 0;
262 }
263
264 /**
265 * Calculate the block offset of an address.
266 * @param addr the address to get the offset of.
267 * @return the block offset.
268 */
269 int extractBlkOffset(Addr addr) const
270 {
271 return (addr & (Addr)(blkSize-1));
272 }
273
274 /**
275 * Regenerate the block address from the tag and the set.
276 * @param tag The tag of the block.
277 * @param set The set the block belongs to.
278 * @return the block address.
279 */
280 Addr regenerateBlkAddr(Addr tag, int set) const
281 {
282 return (tag);
283 }
284
285 /**
286 *iterated through all blocks and clear all locks
287 *Needed to clear all lock tracking at once
288 */
289 virtual void clearLocks();
290};
291
292#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
|