1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a fully associative LRU tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
49#define __MEM_CACHE_TAGS_FA_LRU_HH__
50
51#include <list>
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a fully associative LRU tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
49#define __MEM_CACHE_TAGS_FA_LRU_HH__
50
51#include <list>
|
| 52#include <unordered_map>
|
52
| 53
|
53#include "base/hashmap.hh"
| |
54#include "mem/cache/tags/base.hh"
55#include "mem/cache/blk.hh"
56#include "mem/packet.hh"
57#include "params/FALRU.hh"
58
59/**
60 * A fully associative cache block.
61 */
62class FALRUBlk : public CacheBlk
63{
64public:
65 /** The previous block in LRU order. */
66 FALRUBlk *prev;
67 /** The next block in LRU order. */
68 FALRUBlk *next;
69 /** Has this block been touched? */
70 bool isTouched;
71
72 /**
73 * A bit mask of the sizes of cache that this block is resident in.
74 * Each bit represents a power of 2 in MB size cache.
75 * If bit 0 is set, this block is in a 1MB cache
76 * If bit 2 is set, this block is in a 4MB cache, etc.
77 * There is one bit for each cache smaller than the full size (default
78 * 16MB).
79 */
80 int inCache;
81};
82
83/**
84 * A fully associative LRU cache. Keeps statistics for accesses to a number of
85 * cache sizes at once.
86 */
87class FALRU : public BaseTags
88{
89 public:
90 /** Typedef the block type used in this class. */
91 typedef FALRUBlk BlkType;
92 /** Typedef a list of pointers to the local block type. */
93 typedef std::list<FALRUBlk*> BlkList;
94
95 protected:
96 /** Array of pointers to blocks at the cache size boundaries. */
97 FALRUBlk **cacheBoundaries;
98 /** A mask for the FALRUBlk::inCache bits. */
99 int cacheMask;
100 /** The number of different size caches being tracked. */
101 unsigned numCaches;
102
103 /** The cache blocks. */
104 FALRUBlk *blks;
105
106 /** The MRU block. */
107 FALRUBlk *head;
108 /** The LRU block. */
109 FALRUBlk *tail;
110
111 /** Hash table type mapping addresses to cache block pointers. */
| 54#include "mem/cache/tags/base.hh"
55#include "mem/cache/blk.hh"
56#include "mem/packet.hh"
57#include "params/FALRU.hh"
58
59/**
60 * A fully associative cache block.
61 */
62class FALRUBlk : public CacheBlk
63{
64public:
65 /** The previous block in LRU order. */
66 FALRUBlk *prev;
67 /** The next block in LRU order. */
68 FALRUBlk *next;
69 /** Has this block been touched? */
70 bool isTouched;
71
72 /**
73 * A bit mask of the sizes of cache that this block is resident in.
74 * Each bit represents a power of 2 in MB size cache.
75 * If bit 0 is set, this block is in a 1MB cache
76 * If bit 2 is set, this block is in a 4MB cache, etc.
77 * There is one bit for each cache smaller than the full size (default
78 * 16MB).
79 */
80 int inCache;
81};
82
83/**
84 * A fully associative LRU cache. Keeps statistics for accesses to a number of
85 * cache sizes at once.
86 */
87class FALRU : public BaseTags
88{
89 public:
90 /** Typedef the block type used in this class. */
91 typedef FALRUBlk BlkType;
92 /** Typedef a list of pointers to the local block type. */
93 typedef std::list<FALRUBlk*> BlkList;
94
95 protected:
96 /** Array of pointers to blocks at the cache size boundaries. */
97 FALRUBlk **cacheBoundaries;
98 /** A mask for the FALRUBlk::inCache bits. */
99 int cacheMask;
100 /** The number of different size caches being tracked. */
101 unsigned numCaches;
102
103 /** The cache blocks. */
104 FALRUBlk *blks;
105
106 /** The MRU block. */
107 FALRUBlk *head;
108 /** The LRU block. */
109 FALRUBlk *tail;
110
111 /** Hash table type mapping addresses to cache block pointers. */
|
112 typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t;
| 112 typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t;
|
113 /** Iterator into the address hash table. */
114 typedef hash_t::const_iterator tagIterator;
115
116 /** The address hash table. */
117 hash_t tagHash;
118
119 /**
120 * Find the cache block for the given address.
121 * @param addr The address to find.
122 * @return The cache block of the address, if any.
123 */
124 FALRUBlk * hashLookup(Addr addr) const;
125
126 /**
127 * Move a cache block to the MRU position.
128 * @param blk The block to promote.
129 */
130 void moveToHead(FALRUBlk *blk);
131
132 /**
133 * Check to make sure all the cache boundaries are still where they should
134 * be. Used for debugging.
135 * @return True if everything is correct.
136 */
137 bool check();
138
139 /**
140 * @defgroup FALRUStats Fully Associative LRU specific statistics
141 * The FA lru stack lets us track multiple cache sizes at once. These
142 * statistics track the hits and misses for different cache sizes.
143 * @{
144 */
145
146 /** Hits in each cache size >= 128K. */
147 Stats::Vector hits;
148 /** Misses in each cache size >= 128K. */
149 Stats::Vector misses;
150 /** Total number of accesses. */
151 Stats::Scalar accesses;
152
153 /**
154 * @}
155 */
156
157public:
158
159 typedef FALRUParams Params;
160
161 /**
162 * Construct and initialize this cache tagstore.
163 */
164 FALRU(const Params *p);
165 ~FALRU();
166
167 /**
168 * Register the stats for this object.
169 * @param name The name to prepend to the stats name.
170 */
171 void regStats();
172
173 /**
174 * Invalidate a cache block.
175 * @param blk The block to invalidate.
176 */
177 void invalidate(CacheBlk *blk);
178
179 /**
180 * Access block and update replacement data. May not succeed, in which case
181 * NULL pointer is returned. This has all the implications of a cache
182 * access and should only be used as such.
183 * Returns the access latency and inCache flags as a side effect.
184 * @param addr The address to look for.
185 * @param is_secure True if the target memory space is secure.
186 * @param asid The address space ID.
187 * @param lat The latency of the access.
188 * @param inCache The FALRUBlk::inCache flags.
189 * @return Pointer to the cache block.
190 */
191 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
192 int context_src, int *inCache);
193
194 /**
195 * Just a wrapper of above function to conform with the base interface.
196 */
197 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
198 int context_src);
199
200 /**
201 * Find the block in the cache, do not update the replacement data.
202 * @param addr The address to look for.
203 * @param is_secure True if the target memory space is secure.
204 * @param asid The address space ID.
205 * @return Pointer to the cache block.
206 */
207 CacheBlk* findBlock(Addr addr, bool is_secure) const;
208
209 /**
210 * Find a replacement block for the address provided.
211 * @param pkt The request to a find a replacement candidate for.
212 * @return The block to place the replacement in.
213 */
214 CacheBlk* findVictim(Addr addr);
215
216 void insertBlock(PacketPtr pkt, CacheBlk *blk);
217
218 /**
219 * Return the block size of this cache.
220 * @return The block size.
221 */
222 unsigned
223 getBlockSize() const
224 {
225 return blkSize;
226 }
227
228 /**
229 * Return the subblock size of this cache, always the block size.
230 * @return The block size.
231 */
232 unsigned
233 getSubBlockSize() const
234 {
235 return blkSize;
236 }
237
238 /**
239 * Return the number of sets this cache has
240 * @return The number of sets.
241 */
242 unsigned
243 getNumSets() const
244 {
245 return 1;
246 }
247
248 /**
249 * Return the number of ways this cache has
250 * @return The number of ways.
251 */
252 unsigned
253 getNumWays() const
254 {
255 return numBlocks;
256 }
257
258 /**
259 * Find the cache block given set and way
260 * @param set The set of the block.
261 * @param way The way of the block.
262 * @return The cache block.
263 */
264 CacheBlk* findBlockBySetAndWay(int set, int way) const;
265
266 /**
267 * Align an address to the block size.
268 * @param addr the address to align.
269 * @return The aligned address.
270 */
271 Addr blkAlign(Addr addr) const
272 {
273 return (addr & ~(Addr)(blkSize-1));
274 }
275
276 /**
277 * Generate the tag from the addres. For fully associative this is just the
278 * block address.
279 * @param addr The address to get the tag from.
280 * @return The tag.
281 */
282 Addr extractTag(Addr addr) const
283 {
284 return blkAlign(addr);
285 }
286
287 /**
288 * Return the set of an address. Only one set in a fully associative cache.
289 * @param addr The address to get the set from.
290 * @return 0.
291 */
292 int extractSet(Addr addr) const
293 {
294 return 0;
295 }
296
297 /**
298 * Regenerate the block address from the tag and the set.
299 * @param tag The tag of the block.
300 * @param set The set the block belongs to.
301 * @return the block address.
302 */
303 Addr regenerateBlkAddr(Addr tag, unsigned set) const
304 {
305 return (tag);
306 }
307
308 /**
309 * @todo Implement as in lru. Currently not used
310 */
311 virtual std::string print() const { return ""; }
312
313 /**
314 * Visit each block in the tag store and apply a visitor to the
315 * block.
316 *
317 * The visitor should be a function (or object that behaves like a
318 * function) that takes a cache block reference as its parameter
319 * and returns a bool. A visitor can request the traversal to be
320 * stopped by returning false, returning true causes it to be
321 * called for the next block in the tag store.
322 *
323 * \param visitor Visitor to call on each block.
324 */
| 113 /** Iterator into the address hash table. */
114 typedef hash_t::const_iterator tagIterator;
115
116 /** The address hash table. */
117 hash_t tagHash;
118
119 /**
120 * Find the cache block for the given address.
121 * @param addr The address to find.
122 * @return The cache block of the address, if any.
123 */
124 FALRUBlk * hashLookup(Addr addr) const;
125
126 /**
127 * Move a cache block to the MRU position.
128 * @param blk The block to promote.
129 */
130 void moveToHead(FALRUBlk *blk);
131
132 /**
133 * Check to make sure all the cache boundaries are still where they should
134 * be. Used for debugging.
135 * @return True if everything is correct.
136 */
137 bool check();
138
139 /**
140 * @defgroup FALRUStats Fully Associative LRU specific statistics
141 * The FA lru stack lets us track multiple cache sizes at once. These
142 * statistics track the hits and misses for different cache sizes.
143 * @{
144 */
145
146 /** Hits in each cache size >= 128K. */
147 Stats::Vector hits;
148 /** Misses in each cache size >= 128K. */
149 Stats::Vector misses;
150 /** Total number of accesses. */
151 Stats::Scalar accesses;
152
153 /**
154 * @}
155 */
156
157public:
158
159 typedef FALRUParams Params;
160
161 /**
162 * Construct and initialize this cache tagstore.
163 */
164 FALRU(const Params *p);
165 ~FALRU();
166
167 /**
168 * Register the stats for this object.
169 * @param name The name to prepend to the stats name.
170 */
171 void regStats();
172
173 /**
174 * Invalidate a cache block.
175 * @param blk The block to invalidate.
176 */
177 void invalidate(CacheBlk *blk);
178
179 /**
180 * Access block and update replacement data. May not succeed, in which case
181 * NULL pointer is returned. This has all the implications of a cache
182 * access and should only be used as such.
183 * Returns the access latency and inCache flags as a side effect.
184 * @param addr The address to look for.
185 * @param is_secure True if the target memory space is secure.
186 * @param asid The address space ID.
187 * @param lat The latency of the access.
188 * @param inCache The FALRUBlk::inCache flags.
189 * @return Pointer to the cache block.
190 */
191 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
192 int context_src, int *inCache);
193
194 /**
195 * Just a wrapper of above function to conform with the base interface.
196 */
197 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
198 int context_src);
199
200 /**
201 * Find the block in the cache, do not update the replacement data.
202 * @param addr The address to look for.
203 * @param is_secure True if the target memory space is secure.
204 * @param asid The address space ID.
205 * @return Pointer to the cache block.
206 */
207 CacheBlk* findBlock(Addr addr, bool is_secure) const;
208
209 /**
210 * Find a replacement block for the address provided.
211 * @param pkt The request to a find a replacement candidate for.
212 * @return The block to place the replacement in.
213 */
214 CacheBlk* findVictim(Addr addr);
215
216 void insertBlock(PacketPtr pkt, CacheBlk *blk);
217
218 /**
219 * Return the block size of this cache.
220 * @return The block size.
221 */
222 unsigned
223 getBlockSize() const
224 {
225 return blkSize;
226 }
227
228 /**
229 * Return the subblock size of this cache, always the block size.
230 * @return The block size.
231 */
232 unsigned
233 getSubBlockSize() const
234 {
235 return blkSize;
236 }
237
238 /**
239 * Return the number of sets this cache has
240 * @return The number of sets.
241 */
242 unsigned
243 getNumSets() const
244 {
245 return 1;
246 }
247
248 /**
249 * Return the number of ways this cache has
250 * @return The number of ways.
251 */
252 unsigned
253 getNumWays() const
254 {
255 return numBlocks;
256 }
257
258 /**
259 * Find the cache block given set and way
260 * @param set The set of the block.
261 * @param way The way of the block.
262 * @return The cache block.
263 */
264 CacheBlk* findBlockBySetAndWay(int set, int way) const;
265
266 /**
267 * Align an address to the block size.
268 * @param addr the address to align.
269 * @return The aligned address.
270 */
271 Addr blkAlign(Addr addr) const
272 {
273 return (addr & ~(Addr)(blkSize-1));
274 }
275
276 /**
277 * Generate the tag from the addres. For fully associative this is just the
278 * block address.
279 * @param addr The address to get the tag from.
280 * @return The tag.
281 */
282 Addr extractTag(Addr addr) const
283 {
284 return blkAlign(addr);
285 }
286
287 /**
288 * Return the set of an address. Only one set in a fully associative cache.
289 * @param addr The address to get the set from.
290 * @return 0.
291 */
292 int extractSet(Addr addr) const
293 {
294 return 0;
295 }
296
297 /**
298 * Regenerate the block address from the tag and the set.
299 * @param tag The tag of the block.
300 * @param set The set the block belongs to.
301 * @return the block address.
302 */
303 Addr regenerateBlkAddr(Addr tag, unsigned set) const
304 {
305 return (tag);
306 }
307
308 /**
309 * @todo Implement as in lru. Currently not used
310 */
311 virtual std::string print() const { return ""; }
312
313 /**
314 * Visit each block in the tag store and apply a visitor to the
315 * block.
316 *
317 * The visitor should be a function (or object that behaves like a
318 * function) that takes a cache block reference as its parameter
319 * and returns a bool. A visitor can request the traversal to be
320 * stopped by returning false, returning true causes it to be
321 * called for the next block in the tag store.
322 *
323 * \param visitor Visitor to call on each block.
324 */
|
325 void forEachBlk(CacheBlkVisitor &visitor) M5_ATTR_OVERRIDE {
| 325 void forEachBlk(CacheBlkVisitor &visitor) override {
|
326 for (int i = 0; i < numBlocks; i++) {
327 if (!visitor(blks[i]))
328 return;
329 }
330 }
331
332};
333
334#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
| 326 for (int i = 0; i < numBlocks; i++) {
327 if (!visitor(blks[i]))
328 return;
329 }
330 }
331
332};
333
334#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
|