1/*
2 * Copyright (c) 2012-2013,2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
--- 22 unchanged lines hidden (view full) ---
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a fully associative LRU tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
49#define __MEM_CACHE_TAGS_FA_LRU_HH__
50
51#include <list>
52#include <unordered_map>
53
54#include "mem/cache/base.hh"
55#include "mem/cache/blk.hh"
56#include "mem/cache/tags/base.hh"
57#include "mem/packet.hh"
58#include "params/FALRU.hh"
59
60/**
61 * A fully associative cache block.
62 */
63class FALRUBlk : public CacheBlk
64{
65 public:
66 /** The previous block in LRU order. */
67 FALRUBlk *prev;
68 /** The next block in LRU order. */
69 FALRUBlk *next;
70
71 /**
72 * A bit mask of the sizes of cache that this block is resident in.
73 * Each bit represents a power of 2 in MB size cache.
74 * If bit 0 is set, this block is in a 1MB cache
75 * If bit 2 is set, this block is in a 4MB cache, etc.
76 * There is one bit for each cache smaller than the full size (default
77 * 16MB).
78 */
79 int inCache;
80};
81
82/**
83 * A fully associative LRU cache. Keeps statistics for accesses to a number of
84 * cache sizes at once.
85 */
86class FALRU : public BaseTags
87{
88 public:
89 /** Typedef the block type used in this class. */
90 typedef FALRUBlk BlkType;
91
92 protected:
93 /** Array of pointers to blocks at the cache size boundaries. */
94 FALRUBlk **cacheBoundaries;
95 /** A mask for the FALRUBlk::inCache bits. */
96 int cacheMask;
97 /** The number of different size caches being tracked. */
98 unsigned numCaches;
99
100 /** The cache blocks. */
101 FALRUBlk *blks;
102
103 /** The MRU block. */
104 FALRUBlk *head;
105 /** The LRU block. */
106 FALRUBlk *tail;
107
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129
130 /**
131 * Move a cache block to the LRU position.
132 *
133 * @param blk The block to demote.
134 */
135 void moveToTail(FALRUBlk *blk);
136
137 /**
138 * Check to make sure all the cache boundaries are still where they should
139 * be. Used for debugging.
140 * @return True if everything is correct.
141 */
142 bool check();
143
144 /**
145 * @defgroup FALRUStats Fully Associative LRU specific statistics
146 * The FA lru stack lets us track multiple cache sizes at once. These
147 * statistics track the hits and misses for different cache sizes.
148 * @{
149 */
150
151 /** Hits in each cache size >= 128K. */
152 Stats::Vector hits;
153 /** Misses in each cache size >= 128K. */
154 Stats::Vector misses;
155 /** Total number of accesses. */
156 Stats::Scalar accesses;
157
158 /**
159 * @}
160 */
161
162 public:
163 typedef FALRUParams Params;
164
165 /**
166 * Construct and initialize this cache tagstore.
167 */
168 FALRU(const Params *p);
169 ~FALRU();
170
171 /**
172 * Register the stats for this object.
173 * @param name The name to prepend to the stats name.
174 */
175 void regStats() override;
176
177 /**
178 * Invalidate a cache block.
179 * @param blk The block to invalidate.
180 */
181 void invalidate(CacheBlk *blk) override;
182
183 /**
184 * Access block and update replacement data. May not succeed, in which
185 * case nullptr pointer is returned. This has all the implications of a
186 * cache access and should only be used as such.
187 * Returns the access latency and inCache flags as a side effect.
188 * @param addr The address to look for.
189 * @param is_secure True if the target memory space is secure.
190 * @param lat The latency of the access.
191 * @param inCache The FALRUBlk::inCache flags.
192 * @return Pointer to the cache block.
193 */
194 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
195 int *inCache);
196
197 /**
198 * Just a wrapper of above function to conform with the base interface.
199 */
200 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override;
201
202 /**
203 * Find the block in the cache, do not update the replacement data.
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282 * \param visitor Visitor to call on each block.
283 */
284 void forEachBlk(CacheBlkVisitor &visitor) override {
285 for (int i = 0; i < numBlocks; i++) {
286 if (!visitor(blks[i]))
287 return;
288 }
289 }
290};
291
292#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
2 * Copyright (c) 2012-2013,2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
--- 22 unchanged lines hidden (view full) ---
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a fully associative LRU tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
49#define __MEM_CACHE_TAGS_FA_LRU_HH__
50
51#include <list>
52#include <unordered_map>
53
54#include "mem/cache/base.hh"
55#include "mem/cache/blk.hh"
56#include "mem/cache/tags/base.hh"
57#include "mem/packet.hh"
58#include "params/FALRU.hh"
59
60/**
61 * A fully associative cache block.
62 */
63class FALRUBlk : public CacheBlk
64{
65 public:
66 /** The previous block in LRU order. */
67 FALRUBlk *prev;
68 /** The next block in LRU order. */
69 FALRUBlk *next;
70
71 /**
72 * A bit mask of the sizes of cache that this block is resident in.
73 * Each bit represents a power of 2 in MB size cache.
74 * If bit 0 is set, this block is in a 1MB cache
75 * If bit 2 is set, this block is in a 4MB cache, etc.
76 * There is one bit for each cache smaller than the full size (default
77 * 16MB).
78 */
79 int inCache;
80};
81
82/**
83 * A fully associative LRU cache. Keeps statistics for accesses to a number of
84 * cache sizes at once.
85 */
86class FALRU : public BaseTags
87{
88 public:
89 /** Typedef the block type used in this class. */
90 typedef FALRUBlk BlkType;
91
92 protected:
93 /** Array of pointers to blocks at the cache size boundaries. */
94 FALRUBlk **cacheBoundaries;
95 /** A mask for the FALRUBlk::inCache bits. */
96 int cacheMask;
97 /** The number of different size caches being tracked. */
98 unsigned numCaches;
99
100 /** The cache blocks. */
101 FALRUBlk *blks;
102
103 /** The MRU block. */
104 FALRUBlk *head;
105 /** The LRU block. */
106 FALRUBlk *tail;
107
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129
130 /**
131 * Move a cache block to the LRU position.
132 *
133 * @param blk The block to demote.
134 */
135 void moveToTail(FALRUBlk *blk);
136
137 /**
138 * Check to make sure all the cache boundaries are still where they should
139 * be. Used for debugging.
140 * @return True if everything is correct.
141 */
142 bool check();
143
144 /**
145 * @defgroup FALRUStats Fully Associative LRU specific statistics
146 * The FA lru stack lets us track multiple cache sizes at once. These
147 * statistics track the hits and misses for different cache sizes.
148 * @{
149 */
150
151 /** Hits in each cache size >= 128K. */
152 Stats::Vector hits;
153 /** Misses in each cache size >= 128K. */
154 Stats::Vector misses;
155 /** Total number of accesses. */
156 Stats::Scalar accesses;
157
158 /**
159 * @}
160 */
161
162 public:
163 typedef FALRUParams Params;
164
165 /**
166 * Construct and initialize this cache tagstore.
167 */
168 FALRU(const Params *p);
169 ~FALRU();
170
171 /**
172 * Register the stats for this object.
173 * @param name The name to prepend to the stats name.
174 */
175 void regStats() override;
176
177 /**
178 * Invalidate a cache block.
179 * @param blk The block to invalidate.
180 */
181 void invalidate(CacheBlk *blk) override;
182
183 /**
184 * Access block and update replacement data. May not succeed, in which
185 * case nullptr pointer is returned. This has all the implications of a
186 * cache access and should only be used as such.
187 * Returns the access latency and inCache flags as a side effect.
188 * @param addr The address to look for.
189 * @param is_secure True if the target memory space is secure.
190 * @param lat The latency of the access.
191 * @param inCache The FALRUBlk::inCache flags.
192 * @return Pointer to the cache block.
193 */
194 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
195 int *inCache);
196
197 /**
198 * Just a wrapper of above function to conform with the base interface.
199 */
200 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override;
201
202 /**
203 * Find the block in the cache, do not update the replacement data.
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282 * \param visitor Visitor to call on each block.
283 */
284 void forEachBlk(CacheBlkVisitor &visitor) override {
285 for (int i = 0; i < numBlocks; i++) {
286 if (!visitor(blks[i]))
287 return;
288 }
289 }
290};
291
292#endif // __MEM_CACHE_TAGS_FA_LRU_HH__