1/*
2 * Copyright (c) 2012-2013,2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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57#include "mem/packet.hh"
58#include "params/FALRU.hh"
59
60/**
61 * A fully associative cache block.
62 */
63class FALRUBlk : public CacheBlk
64{
65 public:
66 /** The previous block in LRU order. */
67 FALRUBlk *prev;
68 /** The next block in LRU order. */
69 FALRUBlk *next;
70
71 /**
72 * A bit mask of the sizes of cache that this block is resident in.
73 * Each bit represents a power of 2 in MB size cache.

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146 Stats::Vector misses;
147 /** Total number of accesses. */
148 Stats::Scalar accesses;
149
150 /**
151 * @}
152 */
153
154 public:
155 typedef FALRUParams Params;
156
157 /**
158 * Construct and initialize this cache tagstore.
159 */
160 FALRU(const Params *p);
161 ~FALRU();
162

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203 /**
204 * Find replacement victim based on address.
205 *
206 * @param addr Address to find a victim for.
207 * @return Cache block to be replaced.
208 */
209 CacheBlk* findVictim(Addr addr) override;
210
211 /**
212 * Insert the new block into the cache and update replacement data.
213 *
214 * @param pkt Packet holding the address to update
215 * @param blk The block to update.
216 */
217 void insertBlock(PacketPtr pkt, CacheBlk *blk) override;
218
219 /**
220 * Find the cache block given set and way
221 * @param set The set of the block.
222 * @param way The way of the block.
223 * @return The cache block.
224 */

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274 * \param visitor Visitor to call on each block.
275 */
276 void forEachBlk(CacheBlkVisitor &visitor) override {
277 for (int i = 0; i < numBlocks; i++) {
278 if (!visitor(blks[i]))
279 return;
280 }
281 }
282};
283
284#endif // __MEM_CACHE_TAGS_FA_LRU_HH__