fa_lru.cc (10693:c0979b2ebda5) fa_lru.cc (10815:169af9a2779f)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 147 unchanged lines hidden (view full) ---

156 tagIterator iter = tagHash.find(addr);
157 if (iter != tagHash.end()) {
158 return (*iter).second;
159 }
160 return NULL;
161}
162
163void
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 147 unchanged lines hidden (view full) ---

156 tagIterator iter = tagHash.find(addr);
157 if (iter != tagHash.end()) {
158 return (*iter).second;
159 }
160 return NULL;
161}
162
163void
164FALRU::invalidate(FALRU::BlkType *blk)
164FALRU::invalidate(CacheBlk *blk)
165{
166 assert(blk);
167 tagsInUse--;
168}
169
165{
166 assert(blk);
167 tagsInUse--;
168}
169
170FALRUBlk*
170CacheBlk*
171FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src)
172{
173 return accessBlock(addr, is_secure, lat, context_src, 0);
174}
175
176CacheBlk*
171FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src,
172 int *inCache)
173{
174 accesses++;
175 int tmp_in_cache = 0;
176 Addr blkAddr = blkAlign(addr);
177 FALRUBlk* blk = hashLookup(blkAddr);
178

--- 22 unchanged lines hidden (view full) ---

201 }
202
203 lat = accessLatency;
204 //assert(check());
205 return blk;
206}
207
208
177FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src,
178 int *inCache)
179{
180 accesses++;
181 int tmp_in_cache = 0;
182 Addr blkAddr = blkAlign(addr);
183 FALRUBlk* blk = hashLookup(blkAddr);
184

--- 22 unchanged lines hidden (view full) ---

207 }
208
209 lat = accessLatency;
210 //assert(check());
211 return blk;
212}
213
214
209FALRUBlk*
215CacheBlk*
210FALRU::findBlock(Addr addr, bool is_secure) const
211{
212 Addr blkAddr = blkAlign(addr);
213 FALRUBlk* blk = hashLookup(blkAddr);
214
215 if (blk && blk->isValid()) {
216 assert(blk->tag == blkAddr);
217 } else {
218 blk = NULL;
219 }
220 return blk;
221}
222
216FALRU::findBlock(Addr addr, bool is_secure) const
217{
218 Addr blkAddr = blkAlign(addr);
219 FALRUBlk* blk = hashLookup(blkAddr);
220
221 if (blk && blk->isValid()) {
222 assert(blk->tag == blkAddr);
223 } else {
224 blk = NULL;
225 }
226 return blk;
227}
228
223FALRUBlk*
229CacheBlk*
224FALRU::findVictim(Addr addr)
225{
226 FALRUBlk * blk = tail;
227 assert(blk->inCache == 0);
228 moveToHead(blk);
229 tagHash.erase(blk->tag);
230 tagHash[blkAlign(addr)] = blk;
231 if (blk->isValid()) {

--- 6 unchanged lines hidden (view full) ---

238 warmupCycle = curTick();
239 }
240 }
241 //assert(check());
242 return blk;
243}
244
245void
230FALRU::findVictim(Addr addr)
231{
232 FALRUBlk * blk = tail;
233 assert(blk->inCache == 0);
234 moveToHead(blk);
235 tagHash.erase(blk->tag);
236 tagHash[blkAlign(addr)] = blk;
237 if (blk->isValid()) {

--- 6 unchanged lines hidden (view full) ---

244 warmupCycle = curTick();
245 }
246 }
247 //assert(check());
248 return blk;
249}
250
251void
246FALRU::insertBlock(PacketPtr pkt, FALRU::BlkType *blk)
252FALRU::insertBlock(PacketPtr pkt, CacheBlk *blk)
247{
248}
249
250void
251FALRU::moveToHead(FALRUBlk *blk)
252{
253 int updateMask = blk->inCache ^ cacheMask;
254 for (unsigned i = 0; i < numCaches; i++){

--- 64 unchanged lines hidden --- 		253{
254}
255
256void
257FALRU::moveToHead(FALRUBlk *blk)
258{
259 int updateMask = blk->inCache ^ cacheMask;
260 for (unsigned i = 0; i < numCaches; i++){

--- 64 unchanged lines hidden ---