1/* 2 * Copyright (c) 2013,2016-2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Definitions a fully associative LRU tagstore. 46 */ 47 48#include "mem/cache/tags/fa_lru.hh" 49 50#include <cassert> 51#include <sstream> 52 53#include "base/intmath.hh" 54#include "base/logging.hh" 55
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56using namespace std;
57
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56FALRU::FALRU(const Params *p) 57 : BaseTags(p), cacheBoundaries(nullptr) 58{ 59 if (!isPowerOf2(blkSize)) 60 fatal("cache block size (in bytes) `%d' must be a power of two", 61 blkSize); 62 if (!isPowerOf2(size)) 63 fatal("Cache Size must be power of 2 for now"); 64 65 // Track all cache sizes from 128K up by powers of 2 66 numCaches = floorLog2(size) - 17; 67 if (numCaches >0){ 68 cacheBoundaries = new FALRUBlk *[numCaches]; 69 cacheMask = (ULL(1) << numCaches) - 1; 70 } else { 71 cacheMask = 0; 72 } 73 74 blks = new FALRUBlk[numBlocks]; 75 head = &(blks[0]); 76 tail = &(blks[numBlocks-1]); 77 78 head->prev = nullptr; 79 head->next = &(blks[1]); 80 head->inCache = cacheMask; 81 head->data = &dataBlks[0]; 82 83 tail->prev = &(blks[numBlocks-2]); 84 tail->next = nullptr; 85 tail->inCache = 0; 86 tail->data = &dataBlks[(numBlocks-1)*blkSize]; 87 88 unsigned index = (1 << 17) / blkSize; 89 unsigned j = 0; 90 int flags = cacheMask; 91 for (unsigned i = 1; i < numBlocks - 1; i++) { 92 blks[i].inCache = flags; 93 if (i == index - 1){ 94 cacheBoundaries[j] = &(blks[i]); 95 flags &= ~ (1<<j); 96 ++j; 97 index = index << 1; 98 } 99 blks[i].prev = &(blks[i-1]); 100 blks[i].next = &(blks[i+1]); 101 blks[i].set = 0; 102 blks[i].way = i; 103 104 // Associate a data chunk to the block 105 blks[i].data = &dataBlks[blkSize*i]; 106 } 107 assert(j == numCaches); 108 assert(index == numBlocks); 109 //assert(check()); 110} 111 112FALRU::~FALRU() 113{ 114 if (numCaches) 115 delete[] cacheBoundaries; 116 117 delete[] blks; 118} 119 120void 121FALRU::regStats() 122{
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125 using namespace Stats;
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123 BaseTags::regStats(); 124 hits 125 .init(numCaches+1) 126 .name(name() + ".falru_hits") 127 .desc("The number of hits in each cache size.") 128 ; 129 misses 130 .init(numCaches+1) 131 .name(name() + ".falru_misses") 132 .desc("The number of misses in each cache size.") 133 ; 134 accesses 135 .name(name() + ".falru_accesses") 136 .desc("The number of accesses to the FA LRU cache.") 137 ; 138 139 for (unsigned i = 0; i <= numCaches; ++i) {
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143 stringstream size_str;
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140 std::stringstream size_str; |
141 if (i < 3){ 142 size_str << (1<<(i+7)) <<"K"; 143 } else { 144 size_str << (1<<(i-3)) <<"M"; 145 } 146 147 hits.subname(i, size_str.str()); 148 hits.subdesc(i, "Hits in a " + size_str.str() +" cache"); 149 misses.subname(i, size_str.str()); 150 misses.subdesc(i, "Misses in a " + size_str.str() +" cache"); 151 } 152} 153 154FALRUBlk * 155FALRU::hashLookup(Addr addr) const 156{ 157 tagIterator iter = tagHash.find(addr); 158 if (iter != tagHash.end()) { 159 return (*iter).second; 160 } 161 return nullptr; 162} 163 164void 165FALRU::invalidate(CacheBlk *blk) 166{ 167 // TODO: We need to move the block to the tail to make it the next victim 168 BaseTags::invalidate(blk); 169 170 // Erase block entry in the hash table 171 tagHash.erase(blk->tag); 172} 173 174CacheBlk* 175FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat) 176{ 177 return accessBlock(addr, is_secure, lat, 0); 178} 179 180CacheBlk* 181FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int *inCache) 182{ 183 accesses++; 184 int tmp_in_cache = 0; 185 Addr blkAddr = blkAlign(addr); 186 FALRUBlk* blk = hashLookup(blkAddr); 187 188 if (blk && blk->isValid()) { 189 // If a cache hit 190 lat = accessLatency; 191 // Check if the block to be accessed is available. If not, 192 // apply the accessLatency on top of block->whenReady. 193 if (blk->whenReady > curTick() && 194 cache->ticksToCycles(blk->whenReady - curTick()) > 195 accessLatency) { 196 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 197 accessLatency; 198 } 199 assert(blk->tag == blkAddr); 200 tmp_in_cache = blk->inCache; 201 for (unsigned i = 0; i < numCaches; i++) { 202 if (1<<i & blk->inCache) { 203 hits[i]++; 204 } else { 205 misses[i]++; 206 } 207 } 208 hits[numCaches]++; 209 if (blk != head){ 210 moveToHead(blk); 211 } 212 } else { 213 // If a cache miss 214 lat = lookupLatency; 215 blk = nullptr; 216 for (unsigned i = 0; i <= numCaches; ++i) { 217 misses[i]++; 218 } 219 } 220 if (inCache) { 221 *inCache = tmp_in_cache; 222 } 223 224 //assert(check()); 225 return blk; 226} 227 228 229CacheBlk* 230FALRU::findBlock(Addr addr, bool is_secure) const 231{ 232 Addr blkAddr = blkAlign(addr); 233 FALRUBlk* blk = hashLookup(blkAddr); 234 235 if (blk && blk->isValid()) { 236 assert(blk->tag == blkAddr); 237 } else { 238 blk = nullptr; 239 } 240 return blk; 241} 242 243CacheBlk* 244FALRU::findBlockBySetAndWay(int set, int way) const 245{ 246 assert(set == 0); 247 return &blks[way]; 248} 249 250CacheBlk* 251FALRU::findVictim(Addr addr) 252{ 253 return tail; 254} 255 256void 257FALRU::insertBlock(PacketPtr pkt, CacheBlk *blk) 258{ 259 FALRUBlk* falruBlk = static_cast<FALRUBlk*>(blk); 260 261 // Make sure block is not present in the cache 262 assert(falruBlk->inCache == 0); 263 264 // Do common block insertion functionality 265 BaseTags::insertBlock(pkt, blk); 266 267 // New block is the MRU 268 moveToHead(falruBlk); 269 270 // Insert new block in the hash table 271 tagHash[falruBlk->tag] = falruBlk; 272 273 //assert(check()); 274} 275 276void 277FALRU::moveToHead(FALRUBlk *blk) 278{ 279 int updateMask = blk->inCache ^ cacheMask; 280 for (unsigned i = 0; i < numCaches; i++){ 281 if ((1<<i) & updateMask) { 282 cacheBoundaries[i]->inCache &= ~(1<<i); 283 cacheBoundaries[i] = cacheBoundaries[i]->prev; 284 } else if (cacheBoundaries[i] == blk) { 285 cacheBoundaries[i] = blk->prev; 286 } 287 } 288 blk->inCache = cacheMask; 289 if (blk != head) { 290 if (blk == tail){ 291 assert(blk->next == nullptr); 292 tail = blk->prev; 293 tail->next = nullptr; 294 } else { 295 blk->prev->next = blk->next; 296 blk->next->prev = blk->prev; 297 } 298 blk->next = head; 299 blk->prev = nullptr; 300 head->prev = blk; 301 head = blk; 302 } 303} 304 305bool 306FALRU::check() 307{ 308 FALRUBlk* blk = head; 309 int tot_size = 0; 310 int boundary = 1<<17; 311 int j = 0; 312 int flags = cacheMask; 313 while (blk) { 314 tot_size += blkSize; 315 if (blk->inCache != flags) { 316 return false; 317 } 318 if (tot_size == boundary && blk != tail) { 319 if (cacheBoundaries[j] != blk) { 320 return false; 321 } 322 flags &=~(1 << j); 323 boundary = boundary<<1; 324 ++j; 325 } 326 blk = blk->next; 327 } 328 return true; 329} 330 331FALRU * 332FALRUParams::create() 333{ 334 return new FALRU(this); 335} 336
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