1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Definitions a fully associative LRU tagstore. 46 */ 47 48#include <cassert> 49#include <sstream> 50 51#include "base/intmath.hh" 52#include "base/misc.hh" 53#include "mem/cache/tags/fa_lru.hh" 54 55using namespace std; 56 57FALRU::FALRU(const Params *p) 58 : BaseTags(p), cacheBoundaries(nullptr) 59{ 60 if (!isPowerOf2(blkSize)) 61 fatal("cache block size (in bytes) `%d' must be a power of two", 62 blkSize);
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63 if (!isPowerOf2(size)) 64 fatal("Cache Size must be power of 2 for now"); 65 66 // Track all cache sizes from 128K up by powers of 2 67 numCaches = floorLog2(size) - 17; 68 if (numCaches >0){ 69 cacheBoundaries = new FALRUBlk *[numCaches]; 70 cacheMask = (1 << numCaches) - 1; 71 } else { 72 cacheMask = 0; 73 } 74 75 warmupBound = size/blkSize; 76 numBlocks = size/blkSize; 77 78 blks = new FALRUBlk[numBlocks]; 79 head = &(blks[0]); 80 tail = &(blks[numBlocks-1]); 81 82 head->prev = NULL; 83 head->next = &(blks[1]); 84 head->inCache = cacheMask; 85 86 tail->prev = &(blks[numBlocks-2]); 87 tail->next = NULL; 88 tail->inCache = 0; 89 90 unsigned index = (1 << 17) / blkSize; 91 unsigned j = 0; 92 int flags = cacheMask; 93 for (unsigned i = 1; i < numBlocks - 1; i++) { 94 blks[i].inCache = flags; 95 if (i == index - 1){ 96 cacheBoundaries[j] = &(blks[i]); 97 flags &= ~ (1<<j); 98 ++j; 99 index = index << 1; 100 } 101 blks[i].prev = &(blks[i-1]); 102 blks[i].next = &(blks[i+1]); 103 blks[i].isTouched = false; 104 } 105 assert(j == numCaches); 106 assert(index == numBlocks); 107 //assert(check()); 108} 109 110FALRU::~FALRU() 111{ 112 if (numCaches) 113 delete[] cacheBoundaries; 114 115 delete[] blks; 116} 117 118void 119FALRU::regStats() 120{ 121 using namespace Stats; 122 BaseTags::regStats(); 123 hits 124 .init(numCaches+1) 125 .name(name() + ".falru_hits") 126 .desc("The number of hits in each cache size.") 127 ; 128 misses 129 .init(numCaches+1) 130 .name(name() + ".falru_misses") 131 .desc("The number of misses in each cache size.") 132 ; 133 accesses 134 .name(name() + ".falru_accesses") 135 .desc("The number of accesses to the FA LRU cache.") 136 ; 137 138 for (unsigned i = 0; i <= numCaches; ++i) { 139 stringstream size_str; 140 if (i < 3){ 141 size_str << (1<<(i+7)) <<"K"; 142 } else { 143 size_str << (1<<(i-3)) <<"M"; 144 } 145 146 hits.subname(i, size_str.str()); 147 hits.subdesc(i, "Hits in a " + size_str.str() +" cache"); 148 misses.subname(i, size_str.str()); 149 misses.subdesc(i, "Misses in a " + size_str.str() +" cache"); 150 } 151} 152 153FALRUBlk * 154FALRU::hashLookup(Addr addr) const 155{ 156 tagIterator iter = tagHash.find(addr); 157 if (iter != tagHash.end()) { 158 return (*iter).second; 159 } 160 return NULL; 161} 162 163void 164FALRU::invalidate(FALRU::BlkType *blk) 165{ 166 assert(blk); 167 tagsInUse--; 168} 169 170FALRUBlk* 171FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src, 172 int *inCache) 173{ 174 accesses++; 175 int tmp_in_cache = 0; 176 Addr blkAddr = blkAlign(addr); 177 FALRUBlk* blk = hashLookup(blkAddr); 178 179 if (blk && blk->isValid()) { 180 assert(blk->tag == blkAddr); 181 tmp_in_cache = blk->inCache; 182 for (unsigned i = 0; i < numCaches; i++) { 183 if (1<<i & blk->inCache) { 184 hits[i]++; 185 } else { 186 misses[i]++; 187 } 188 } 189 hits[numCaches]++; 190 if (blk != head){ 191 moveToHead(blk); 192 } 193 } else { 194 blk = NULL; 195 for (unsigned i = 0; i <= numCaches; ++i) { 196 misses[i]++; 197 } 198 } 199 if (inCache) { 200 *inCache = tmp_in_cache; 201 } 202
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