fa_lru.cc (10360:919c02740209) | fa_lru.cc (10693:c0979b2ebda5) |
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1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 46 unchanged lines hidden (view full) --- 55using namespace std; 56 57FALRU::FALRU(const Params *p) 58 : BaseTags(p), cacheBoundaries(nullptr) 59{ 60 if (!isPowerOf2(blkSize)) 61 fatal("cache block size (in bytes) `%d' must be a power of two", 62 blkSize); | 1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 46 unchanged lines hidden (view full) --- 55using namespace std; 56 57FALRU::FALRU(const Params *p) 58 : BaseTags(p), cacheBoundaries(nullptr) 59{ 60 if (!isPowerOf2(blkSize)) 61 fatal("cache block size (in bytes) `%d' must be a power of two", 62 blkSize); |
63 if (!(hitLatency > 0)) 64 fatal("Access latency in cycles must be at least one cycle"); | |
65 if (!isPowerOf2(size)) 66 fatal("Cache Size must be power of 2 for now"); 67 68 // Track all cache sizes from 128K up by powers of 2 69 numCaches = floorLog2(size) - 17; 70 if (numCaches >0){ 71 cacheBoundaries = new FALRUBlk *[numCaches]; 72 cacheMask = (1 << numCaches) - 1; --- 124 unchanged lines hidden (view full) --- 197 for (unsigned i = 0; i <= numCaches; ++i) { 198 misses[i]++; 199 } 200 } 201 if (inCache) { 202 *inCache = tmp_in_cache; 203 } 204 | 63 if (!isPowerOf2(size)) 64 fatal("Cache Size must be power of 2 for now"); 65 66 // Track all cache sizes from 128K up by powers of 2 67 numCaches = floorLog2(size) - 17; 68 if (numCaches >0){ 69 cacheBoundaries = new FALRUBlk *[numCaches]; 70 cacheMask = (1 << numCaches) - 1; --- 124 unchanged lines hidden (view full) --- 195 for (unsigned i = 0; i <= numCaches; ++i) { 196 misses[i]++; 197 } 198 } 199 if (inCache) { 200 *inCache = tmp_in_cache; 201 } 202 |
205 lat = hitLatency; | 203 lat = accessLatency; |
206 //assert(check()); 207 return blk; 208} 209 210 211FALRUBlk* 212FALRU::findBlock(Addr addr, bool is_secure) const 213{ --- 107 unchanged lines hidden --- | 204 //assert(check()); 205 return blk; 206} 207 208 209FALRUBlk* 210FALRU::findBlock(Addr addr, bool is_secure) const 211{ --- 107 unchanged lines hidden --- |