1/*
2 * Copyright (c) 2013,2016-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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93 if (i == index - 1){
94 cacheBoundaries[j] = &(blks[i]);
95 flags &= ~ (1<<j);
96 ++j;
97 index = index << 1;
98 }
99 blks[i].prev = &(blks[i-1]);
100 blks[i].next = &(blks[i+1]);
101 blks[i].set = 0;
102 blks[i].way = i;
103 }
104 assert(j == numCaches);
105 assert(index == numBlocks);
106 //assert(check());
107}
108

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249 assert(blk->inCache == 0);
250 moveToHead(blk);
251 tagHash.erase(blk->tag);
252 tagHash[blkAlign(addr)] = blk;
253 if (blk->isValid()) {
254 replacements[0]++;
255 } else {
256 tagsInUse++;
257 if (!warmedUp && tagsInUse.value() >= warmupBound) {
258 warmedUp = true;
259 warmupCycle = curTick();
260 }
261 }
262 //assert(check());
263
264 return blk;
265}
266
267void
268FALRU::insertBlock(PacketPtr pkt, CacheBlk *blk)
269{
270}
271

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