1/*
2 * Copyright (c) 2018 Inria
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37#define __MEM_CACHE_TAGS_COMPRESSED_TAGS_HH__
38
39#include <vector>
40
41#include "mem/cache/tags/sector_tags.hh"
42#include "mem/cache/tags/super_blk.hh"
43
44class BaseCache;
45struct CompressedTagsParams;
46
47/**
48 * A CompressedTags cache tag store.
49 * @sa \ref gem5MemorySystem "gem5 Memory System"
50 *
51 * The Compression Ratio (CR) of a superblock is defined by
52 * CR = uncompressed_size / compressed_size.

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92 virtual ~CompressedTags() {};
93
94 /**
95 * Initialize blocks as SuperBlk and CompressionBlk instances.
96 */
97 void tagsInit() override;
98
99 /**
100 * Insert the new block into the cache and update replacement data.
101 *
102 * @param pkt Packet holding the address to update
103 * @param blk The block to update.
104 */
105 void insertBlock(const PacketPtr pkt, CacheBlk *blk) override;
106
107 /**

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