base_set_assoc.hh (10815:169af9a2779f) base_set_assoc.hh (10941:a39646f4c407)
1/*
1/*
2 * Copyright (c) 2012-2013 ARM Limited
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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82 typedef std::list<BlkType*> BlkList;
83 /** Typedef the set type used in this tag store. */
84 typedef CacheSet<CacheBlk> SetType;
85
86
87 protected:
88 /** The associativity of the cache. */
89 const unsigned assoc;
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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82 typedef std::list<BlkType*> BlkList;
83 /** Typedef the set type used in this tag store. */
84 typedef CacheSet<CacheBlk> SetType;
85
86
87 protected:
88 /** The associativity of the cache. */
89 const unsigned assoc;
90 /** The allocatable associativity of the cache (alloc mask). */
91 unsigned allocAssoc;
90 /** The number of sets in the cache. */
91 const unsigned numSets;
92 /** Whether tags and data are accessed sequentially. */
93 const bool sequentialAccess;
94
95 /** The cache sets. */
96 SetType *sets;
97

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141 */
142 unsigned
143 getSubBlockSize() const
144 {
145 return blkSize;
146 }
147
148 /**
92 /** The number of sets in the cache. */
93 const unsigned numSets;
94 /** Whether tags and data are accessed sequentially. */
95 const bool sequentialAccess;
96
97 /** The cache sets. */
98 SetType *sets;
99

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143 */
144 unsigned
145 getSubBlockSize() const
146 {
147 return blkSize;
148 }
149
150 /**
151 * Return the number of sets this cache has
152 * @return The number of sets.
153 */
154 unsigned
155 getNumSets() const
156 {
157 return numSets;
158 }
159
160 /**
161 * Return the number of ways this cache has
162 * @return The number of ways.
163 */
164 unsigned
165 getNumWays() const
166 {
167 return assoc;
168 }
169
170 /**
171 * Find the cache block given set and way
172 * @param set The set of the block.
173 * @param way The way of the block.
174 * @return The cache block.
175 */
176 CacheBlk *findBlockBySetAndWay(int set, int way) const;
177
178 /**
149 * Invalidate the given block.
150 * @param blk The block to invalidate.
151 */
152 void invalidate(CacheBlk *blk)
153 {
154 assert(blk);
155 assert(blk->isValid());
156 tagsInUse--;

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178 Addr tag = extractTag(addr);
179 int set = extractSet(addr);
180 BlkType *blk = sets[set].findBlk(tag, is_secure);
181 lat = accessLatency;;
182
183 // Access all tags in parallel, hence one in each way. The data side
184 // either accesses all blocks in parallel, or one block sequentially on
185 // a hit. Sequential access with a miss doesn't access data.
179 * Invalidate the given block.
180 * @param blk The block to invalidate.
181 */
182 void invalidate(CacheBlk *blk)
183 {
184 assert(blk);
185 assert(blk->isValid());
186 tagsInUse--;

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208 Addr tag = extractTag(addr);
209 int set = extractSet(addr);
210 BlkType *blk = sets[set].findBlk(tag, is_secure);
211 lat = accessLatency;;
212
213 // Access all tags in parallel, hence one in each way. The data side
214 // either accesses all blocks in parallel, or one block sequentially on
215 // a hit. Sequential access with a miss doesn't access data.
186 tagAccesses += assoc;
216 tagAccesses += allocAssoc;
187 if (sequentialAccess) {
188 if (blk != NULL) {
189 dataAccesses += 1;
190 }
191 } else {
217 if (sequentialAccess) {
218 if (blk != NULL) {
219 dataAccesses += 1;
220 }
221 } else {
192 dataAccesses += assoc;
222 dataAccesses += allocAssoc;
193 }
194
195 if (blk != NULL) {
196 if (blk->whenReady > curTick()
197 && cache->ticksToCycles(blk->whenReady - curTick())
198 > accessLatency) {
199 lat = cache->ticksToCycles(blk->whenReady - curTick());
200 }

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222 * @return The candidate block.
223 */
224 CacheBlk* findVictim(Addr addr)
225 {
226 BlkType *blk = NULL;
227 int set = extractSet(addr);
228
229 // prefer to evict an invalid block
223 }
224
225 if (blk != NULL) {
226 if (blk->whenReady > curTick()
227 && cache->ticksToCycles(blk->whenReady - curTick())
228 > accessLatency) {
229 lat = cache->ticksToCycles(blk->whenReady - curTick());
230 }

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252 * @return The candidate block.
253 */
254 CacheBlk* findVictim(Addr addr)
255 {
256 BlkType *blk = NULL;
257 int set = extractSet(addr);
258
259 // prefer to evict an invalid block
230 for (int i = 0; i < assoc; ++i) {
260 for (int i = 0; i < allocAssoc; ++i) {
231 blk = sets[set].blks[i];
261 blk = sets[set].blks[i];
232 if (!blk->isValid()) {
262 if (!blk->isValid())
233 break;
263 break;
234 }
235 }
236
237 return blk;
238 }
239
240 /**
241 * Insert the new block into the cache.
242 * @param pkt Packet holding the address to update

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287 blk->tickInserted = curTick();
288
289 // We only need to write into one tag and one data block.
290 tagAccesses += 1;
291 dataAccesses += 1;
292 }
293
294 /**
264 }
265
266 return blk;
267 }
268
269 /**
270 * Insert the new block into the cache.
271 * @param pkt Packet holding the address to update

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316 blk->tickInserted = curTick();
317
318 // We only need to write into one tag and one data block.
319 tagAccesses += 1;
320 dataAccesses += 1;
321 }
322
323 /**
324 * Limit the allocation for the cache ways.
325 * @param ways The maximum number of ways available for replacement.
326 */
327 virtual void setWayAllocationMax(int ways)
328 {
329 fatal_if(ways < 1, "Allocation limit must be greater than zero");
330 allocAssoc = ways;
331 }
332
333 /**
334 * Get the way allocation mask limit.
335 * @return The maximum number of ways available for replacement.
336 */
337 virtual int getWayAllocationMax() const
338 {
339 return allocAssoc;
340 }
341
342 /**
295 * Generate the tag from the given address.
296 * @param addr The address to get the tag from.
297 * @return The tag of the address.
298 */
299 Addr extractTag(Addr addr) const
300 {
301 return (addr >> tagShift);
302 }

--- 74 unchanged lines hidden --- 		343 * Generate the tag from the given address.
344 * @param addr The address to get the tag from.
345 * @return The tag of the address.
346 */
347 Addr extractTag(Addr addr) const
348 {
349 return (addr >> tagShift);
350 }

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