base_set_assoc.hh (10693:c0979b2ebda5) base_set_assoc.hh (10815:169af9a2779f)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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144 {
145 return blkSize;
146 }
147
148 /**
149 * Invalidate the given block.
150 * @param blk The block to invalidate.
151 */
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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144 {
145 return blkSize;
146 }
147
148 /**
149 * Invalidate the given block.
150 * @param blk The block to invalidate.
151 */
152 void invalidate(BlkType *blk)
152 void invalidate(CacheBlk *blk)
153 {
154 assert(blk);
155 assert(blk->isValid());
156 tagsInUse--;
157 assert(blk->srcMasterId < cache->system->maxMasters());
158 occupancies[blk->srcMasterId]--;
159 blk->srcMasterId = Request::invldMasterId;
160 blk->task_id = ContextSwitchTaskId::Unknown;

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167 * access and should only be used as such. Returns the access latency as a
168 * side effect.
169 * @param addr The address to find.
170 * @param is_secure True if the target memory space is secure.
171 * @param asid The address space ID.
172 * @param lat The access latency.
173 * @return Pointer to the cache block if found.
174 */
153 {
154 assert(blk);
155 assert(blk->isValid());
156 tagsInUse--;
157 assert(blk->srcMasterId < cache->system->maxMasters());
158 occupancies[blk->srcMasterId]--;
159 blk->srcMasterId = Request::invldMasterId;
160 blk->task_id = ContextSwitchTaskId::Unknown;

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167 * access and should only be used as such. Returns the access latency as a
168 * side effect.
169 * @param addr The address to find.
170 * @param is_secure True if the target memory space is secure.
171 * @param asid The address space ID.
172 * @param lat The access latency.
173 * @return Pointer to the cache block if found.
174 */
175 BlkType* accessBlock(Addr addr, bool is_secure, Cycles &lat,
175 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
176 int context_src)
177 {
178 Addr tag = extractTag(addr);
179 int set = extractSet(addr);
180 BlkType *blk = sets[set].findBlk(tag, is_secure);
181 lat = accessLatency;;
182
183 // Access all tags in parallel, hence one in each way. The data side

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207 /**
208 * Finds the given address in the cache, do not update replacement data.
209 * i.e. This is a no-side-effect find of a block.
210 * @param addr The address to find.
211 * @param is_secure True if the target memory space is secure.
212 * @param asid The address space ID.
213 * @return Pointer to the cache block if found.
214 */
176 int context_src)
177 {
178 Addr tag = extractTag(addr);
179 int set = extractSet(addr);
180 BlkType *blk = sets[set].findBlk(tag, is_secure);
181 lat = accessLatency;;
182
183 // Access all tags in parallel, hence one in each way. The data side

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207 /**
208 * Finds the given address in the cache, do not update replacement data.
209 * i.e. This is a no-side-effect find of a block.
210 * @param addr The address to find.
211 * @param is_secure True if the target memory space is secure.
212 * @param asid The address space ID.
213 * @return Pointer to the cache block if found.
214 */
215 BlkType* findBlock(Addr addr, bool is_secure) const;
215 CacheBlk* findBlock(Addr addr, bool is_secure) const;
216
217 /**
218 * Find an invalid block to evict for the address provided.
219 * If there are no invalid blocks, this will return the block
220 * in the least-recently-used position.
221 * @param addr The addr to a find a replacement candidate for.
222 * @return The candidate block.
223 */
216
217 /**
218 * Find an invalid block to evict for the address provided.
219 * If there are no invalid blocks, this will return the block
220 * in the least-recently-used position.
221 * @param addr The addr to a find a replacement candidate for.
222 * @return The candidate block.
223 */
224 BlkType* findVictim(Addr addr) const
224 CacheBlk* findVictim(Addr addr)
225 {
226 BlkType *blk = NULL;
227 int set = extractSet(addr);
228
229 // prefer to evict an invalid block
230 for (int i = 0; i < assoc; ++i) {
231 blk = sets[set].blks[i];
232 if (!blk->isValid()) {

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237 return blk;
238 }
239
240 /**
241 * Insert the new block into the cache.
242 * @param pkt Packet holding the address to update
243 * @param blk The block to update.
244 */
225 {
226 BlkType *blk = NULL;
227 int set = extractSet(addr);
228
229 // prefer to evict an invalid block
230 for (int i = 0; i < assoc; ++i) {
231 blk = sets[set].blks[i];
232 if (!blk->isValid()) {

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237 return blk;
238 }
239
240 /**
241 * Insert the new block into the cache.
242 * @param pkt Packet holding the address to update
243 * @param blk The block to update.
244 */
245 void insertBlock(PacketPtr pkt, BlkType *blk)
245 void insertBlock(PacketPtr pkt, CacheBlk *blk)
246 {
247 Addr addr = pkt->getAddr();
248 MasterID master_id = pkt->req->masterId();
249 uint32_t task_id = pkt->req->taskId();
250
251 if (!blk->isTouched) {
252 tagsInUse++;
253 blk->isTouched = true;

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307 * @return The set index of the address.
308 */
309 int extractSet(Addr addr) const
310 {
311 return ((addr >> setShift) & setMask);
312 }
313
314 /**
246 {
247 Addr addr = pkt->getAddr();
248 MasterID master_id = pkt->req->masterId();
249 uint32_t task_id = pkt->req->taskId();
250
251 if (!blk->isTouched) {
252 tagsInUse++;
253 blk->isTouched = true;

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307 * @return The set index of the address.
308 */
309 int extractSet(Addr addr) const
310 {
311 return ((addr >> setShift) & setMask);
312 }
313
314 /**
315 * Get the block offset from an address.
316 * @param addr The address to get the offset of.
317 * @return The block offset.
318 */
319 int extractBlkOffset(Addr addr) const
320 {
321 return (addr & blkMask);
322 }
323
324 /**
325 * Align an address to the block size.
326 * @param addr the address to align.
327 * @return The block address.
328 */
329 Addr blkAlign(Addr addr) const
330 {
331 return (addr & ~(Addr)blkMask);
332 }

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370 * The visitor should be a function (or object that behaves like a
371 * function) that takes a cache block reference as its parameter
372 * and returns a bool. A visitor can request the traversal to be
373 * stopped by returning false, returning true causes it to be
374 * called for the next block in the tag store.
375 *
376 * \param visitor Visitor to call on each block.
377 */
315 * Align an address to the block size.
316 * @param addr the address to align.
317 * @return The block address.
318 */
319 Addr blkAlign(Addr addr) const
320 {
321 return (addr & ~(Addr)blkMask);
322 }

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360 * The visitor should be a function (or object that behaves like a
361 * function) that takes a cache block reference as its parameter
362 * and returns a bool. A visitor can request the traversal to be
363 * stopped by returning false, returning true causes it to be
364 * called for the next block in the tag store.
365 *
366 * \param visitor Visitor to call on each block.
367 */
378 template <typename V>
379 void forEachBlk(V &visitor) {
368 void forEachBlk(CacheBlkVisitor &visitor) M5_ATTR_OVERRIDE {
380 for (unsigned i = 0; i < numSets * assoc; ++i) {
381 if (!visitor(blks[i]))
382 return;
383 }
384 }
385};
386
387#endif // __MEM_CACHE_TAGS_BASESETASSOC_HH__
369 for (unsigned i = 0; i < numSets * assoc; ++i) {
370 if (!visitor(blks[i]))
371 return;
372 }
373 }
374};
375
376#endif // __MEM_CACHE_TAGS_BASESETASSOC_HH__