1/* 2 * Copyright (c) 2012-2014,2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a base set associative tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 50 51#include <functional> 52#include <string> 53#include <vector> 54 55#include "base/logging.hh" 56#include "base/types.hh" 57#include "mem/cache/base.hh" 58#include "mem/cache/cache_blk.hh" 59#include "mem/cache/replacement_policies/base.hh" 60#include "mem/cache/replacement_policies/replaceable_entry.hh" 61#include "mem/cache/tags/base.hh" 62#include "mem/cache/tags/indexing_policies/base.hh"
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63#include "mem/packet.hh" |
64#include "params/BaseSetAssoc.hh" 65 66/** 67 * A basic cache tag store. 68 * @sa \ref gem5MemorySystem "gem5 Memory System" 69 * 70 * The BaseSetAssoc placement policy divides the cache into s sets of w 71 * cache lines (ways). 72 */ 73class BaseSetAssoc : public BaseTags 74{ 75 protected: 76 /** The allocatable associativity of the cache (alloc mask). */ 77 unsigned allocAssoc; 78 79 /** The cache blocks. */ 80 std::vector<CacheBlk> blks; 81 82 /** Whether tags and data are accessed sequentially. */ 83 const bool sequentialAccess; 84 85 /** Replacement policy */ 86 BaseReplacementPolicy *replacementPolicy; 87 88 public: 89 /** Convenience typedef. */ 90 typedef BaseSetAssocParams Params; 91 92 /** 93 * Construct and initialize this tag store. 94 */ 95 BaseSetAssoc(const Params *p); 96 97 /** 98 * Destructor 99 */ 100 virtual ~BaseSetAssoc() {}; 101 102 /** 103 * Initialize blocks as CacheBlk instances. 104 */ 105 void tagsInit() override; 106 107 /** 108 * This function updates the tags when a block is invalidated. It also 109 * updates the replacement data. 110 * 111 * @param blk The block to invalidate. 112 */ 113 void invalidate(CacheBlk *blk) override; 114 115 /** 116 * Access block and update replacement data. May not succeed, in which case 117 * nullptr is returned. This has all the implications of a cache access and 118 * should only be used as such. Returns the tag lookup latency as a side 119 * effect. 120 * 121 * @param addr The address to find. 122 * @param is_secure True if the target memory space is secure. 123 * @param lat The latency of the tag lookup. 124 * @return Pointer to the cache block if found. 125 */ 126 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 127 { 128 CacheBlk *blk = findBlock(addr, is_secure); 129 130 // Access all tags in parallel, hence one in each way. The data side 131 // either accesses all blocks in parallel, or one block sequentially on 132 // a hit. Sequential access with a miss doesn't access data. 133 tagAccesses += allocAssoc; 134 if (sequentialAccess) { 135 if (blk != nullptr) { 136 dataAccesses += 1; 137 } 138 } else { 139 dataAccesses += allocAssoc; 140 } 141 142 // If a cache hit 143 if (blk != nullptr) { 144 // Update number of references to accessed block 145 blk->refCount++; 146 147 // Update replacement data of accessed block 148 replacementPolicy->touch(blk->replacementData); 149 } 150 151 // The tag lookup latency is the same for a hit or a miss 152 lat = lookupLatency; 153 154 return blk; 155 } 156 157 /** 158 * Find replacement victim based on address. The list of evicted blocks 159 * only contains the victim. 160 * 161 * @param addr Address to find a victim for. 162 * @param is_secure True if the target memory space is secure. 163 * @param evict_blks Cache blocks to be evicted. 164 * @return Cache block to be replaced. 165 */ 166 CacheBlk* findVictim(Addr addr, const bool is_secure, 167 std::vector<CacheBlk*>& evict_blks) const override 168 { 169 // Get possible entries to be victimized 170 const std::vector<ReplaceableEntry*> entries = 171 indexingPolicy->getPossibleEntries(addr); 172 173 // Choose replacement victim from replacement candidates 174 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim( 175 entries)); 176 177 // There is only one eviction for this replacement 178 evict_blks.push_back(victim); 179 180 return victim; 181 } 182 183 /** 184 * Insert the new block into the cache and update replacement data. 185 *
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185 * @param addr Address of the block.
186 * @param is_secure Whether the block is in secure space or not.
187 * @param src_master_ID The source requestor ID.
188 * @param task_ID The new task ID.
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186 * @param pkt Packet holding the address to update |
187 * @param blk The block to update. 188 */
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191 void insertBlock(const Addr addr, const bool is_secure,
192 const int src_master_ID, const uint32_t task_ID,
193 CacheBlk *blk) override
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189 void insertBlock(const PacketPtr pkt, CacheBlk *blk) override |
190 { 191 // Insert block
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196 BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk);
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192 BaseTags::insertBlock(pkt, blk); |
193 194 // Increment tag counter 195 tagsInUse++; 196 197 // Update replacement policy 198 replacementPolicy->reset(blk->replacementData); 199 } 200 201 /** 202 * Limit the allocation for the cache ways. 203 * @param ways The maximum number of ways available for replacement. 204 */ 205 virtual void setWayAllocationMax(int ways) override 206 { 207 fatal_if(ways < 1, "Allocation limit must be greater than zero"); 208 allocAssoc = ways; 209 } 210 211 /** 212 * Get the way allocation mask limit. 213 * @return The maximum number of ways available for replacement. 214 */ 215 virtual int getWayAllocationMax() const override 216 { 217 return allocAssoc; 218 } 219 220 /** 221 * Regenerate the block address from the tag and indexing location. 222 * 223 * @param block The block. 224 * @return the block address. 225 */ 226 Addr regenerateBlkAddr(const CacheBlk* blk) const override 227 { 228 return indexingPolicy->regenerateAddr(blk->tag, blk); 229 } 230 231 void forEachBlk(std::function<void(CacheBlk &)> visitor) override { 232 for (CacheBlk& blk : blks) { 233 visitor(blk); 234 } 235 } 236 237 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override { 238 for (CacheBlk& blk : blks) { 239 if (visitor(blk)) { 240 return true; 241 } 242 } 243 return false; 244 } 245}; 246 247#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
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