1/* 2 * Copyright (c) 2012-2014,2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a base set associative tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 50 51#include <functional> 52#include <string> 53#include <vector> 54 55#include "base/logging.hh" 56#include "base/types.hh" 57#include "mem/cache/base.hh" 58#include "mem/cache/cache_blk.hh" 59#include "mem/cache/replacement_policies/base.hh" 60#include "mem/cache/replacement_policies/replaceable_entry.hh" 61#include "mem/cache/tags/base.hh" 62#include "mem/cache/tags/indexing_policies/base.hh" 63#include "params/BaseSetAssoc.hh" 64 65/** 66 * A basic cache tag store. 67 * @sa \ref gem5MemorySystem "gem5 Memory System" 68 * 69 * The BaseSetAssoc placement policy divides the cache into s sets of w 70 * cache lines (ways). 71 */ 72class BaseSetAssoc : public BaseTags 73{ 74 protected: 75 /** The allocatable associativity of the cache (alloc mask). */ 76 unsigned allocAssoc; 77 78 /** The cache blocks. */ 79 std::vector<CacheBlk> blks; 80 81 /** Whether tags and data are accessed sequentially. */ 82 const bool sequentialAccess; 83 84 /** Replacement policy */ 85 BaseReplacementPolicy *replacementPolicy; 86 87 public: 88 /** Convenience typedef. */ 89 typedef BaseSetAssocParams Params; 90 91 /** 92 * Construct and initialize this tag store. 93 */ 94 BaseSetAssoc(const Params *p); 95 96 /** 97 * Destructor 98 */ 99 virtual ~BaseSetAssoc() {}; 100 101 /** 102 * Initialize blocks and set the parent cache back pointer. 103 * 104 * @param _cache Pointer to parent cache. 105 */ 106 void tagsInit(BaseCache *_cache) override; 107 108 /** 109 * This function updates the tags when a block is invalidated. It also 110 * updates the replacement data. 111 * 112 * @param blk The block to invalidate. 113 */ 114 void invalidate(CacheBlk *blk) override; 115 116 /** 117 * Access block and update replacement data. May not succeed, in which case
|
118 * nullptr is returned. This has all the implications of a cache
119 * access and should only be used as such. Returns the access latency as a
120 * side effect.
|
118 * nullptr is returned. This has all the implications of a cache access and 119 * should only be used as such. Returns the tag lookup latency as a side 120 * effect. 121 * |
122 * @param addr The address to find. 123 * @param is_secure True if the target memory space is secure.
|
123 * @param lat The access latency.
|
124 * @param lat The latency of the tag lookup. |
125 * @return Pointer to the cache block if found. 126 */ 127 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 128 { 129 CacheBlk *blk = findBlock(addr, is_secure); 130 131 // Access all tags in parallel, hence one in each way. The data side 132 // either accesses all blocks in parallel, or one block sequentially on 133 // a hit. Sequential access with a miss doesn't access data. 134 tagAccesses += allocAssoc; 135 if (sequentialAccess) { 136 if (blk != nullptr) { 137 dataAccesses += 1; 138 } 139 } else { 140 dataAccesses += allocAssoc; 141 } 142
|
143 // If a cache hit |
144 if (blk != nullptr) {
|
143 // If a cache hit
144 lat = accessLatency;
145 // Check if the block to be accessed is available. If not,
146 // apply the accessLatency on top of block->whenReady.
147 if (blk->whenReady > curTick() &&
148 cache->ticksToCycles(blk->whenReady - curTick()) >
149 accessLatency) {
150 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
151 accessLatency;
152 }
153
|
145 // Update number of references to accessed block 146 blk->refCount++; 147 148 // Update replacement data of accessed block 149 replacementPolicy->touch(blk->replacementData);
|
159 } else {
160 // If a cache miss
161 lat = lookupLatency;
|
150 } 151
|
152 // The tag lookup latency is the same for a hit or a miss 153 lat = lookupLatency; 154 |
155 return blk; 156 } 157 158 /** 159 * Find replacement victim based on address. The list of evicted blocks 160 * only contains the victim. 161 * 162 * @param addr Address to find a victim for. 163 * @param is_secure True if the target memory space is secure. 164 * @param evict_blks Cache blocks to be evicted. 165 * @return Cache block to be replaced. 166 */ 167 CacheBlk* findVictim(Addr addr, const bool is_secure, 168 std::vector<CacheBlk*>& evict_blks) const override 169 { 170 // Get possible entries to be victimized 171 const std::vector<ReplaceableEntry*> entries = 172 indexingPolicy->getPossibleEntries(addr); 173 174 // Choose replacement victim from replacement candidates 175 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim( 176 entries)); 177 178 // There is only one eviction for this replacement 179 evict_blks.push_back(victim); 180 181 return victim; 182 } 183 184 /** 185 * Insert the new block into the cache and update replacement data. 186 * 187 * @param addr Address of the block. 188 * @param is_secure Whether the block is in secure space or not. 189 * @param src_master_ID The source requestor ID. 190 * @param task_ID The new task ID. 191 * @param blk The block to update. 192 */ 193 void insertBlock(const Addr addr, const bool is_secure, 194 const int src_master_ID, const uint32_t task_ID, 195 CacheBlk *blk) override 196 { 197 // Insert block 198 BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk); 199 200 // Increment tag counter 201 tagsInUse++; 202 203 // Update replacement policy 204 replacementPolicy->reset(blk->replacementData); 205 } 206 207 /** 208 * Limit the allocation for the cache ways. 209 * @param ways The maximum number of ways available for replacement. 210 */ 211 virtual void setWayAllocationMax(int ways) override 212 { 213 fatal_if(ways < 1, "Allocation limit must be greater than zero"); 214 allocAssoc = ways; 215 } 216 217 /** 218 * Get the way allocation mask limit. 219 * @return The maximum number of ways available for replacement. 220 */ 221 virtual int getWayAllocationMax() const override 222 { 223 return allocAssoc; 224 } 225 226 /** 227 * Regenerate the block address from the tag and indexing location. 228 * 229 * @param block The block. 230 * @return the block address. 231 */ 232 Addr regenerateBlkAddr(const CacheBlk* blk) const override 233 { 234 return indexingPolicy->regenerateAddr(blk->tag, blk); 235 } 236 237 void forEachBlk(std::function<void(CacheBlk &)> visitor) override { 238 for (CacheBlk& blk : blks) { 239 visitor(blk); 240 } 241 } 242 243 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override { 244 for (CacheBlk& blk : blks) { 245 if (visitor(blk)) { 246 return true; 247 } 248 } 249 return false; 250 } 251}; 252 253#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
|