1/* 2 * Copyright (c) 2012-2014,2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a base set associative tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 50 51#include <cassert> 52#include <cstring> 53#include <memory> 54#include <vector> 55 56#include "mem/cache/base.hh" 57#include "mem/cache/blk.hh" 58#include "mem/cache/tags/base.hh" 59#include "mem/cache/tags/cacheset.hh" 60#include "mem/packet.hh" 61#include "params/BaseSetAssoc.hh" 62 63/** 64 * A BaseSetAssoc cache tag store. 65 * @sa \ref gem5MemorySystem "gem5 Memory System" 66 * 67 * The BaseSetAssoc placement policy divides the cache into s sets of w 68 * cache lines (ways). A cache line is mapped onto a set, and can be placed 69 * into any of the ways of this set. 70 */ 71class BaseSetAssoc : public BaseTags 72{ 73 public: 74 /** Typedef the block type used in this tag store. */ 75 typedef CacheBlk BlkType; 76 /** Typedef the set type used in this tag store. */ 77 typedef CacheSet<CacheBlk> SetType; 78 79 protected: 80 /** The associativity of the cache. */ 81 const unsigned assoc; 82 /** The allocatable associativity of the cache (alloc mask). */ 83 unsigned allocAssoc; 84 85 /** The cache blocks. */ 86 std::vector<BlkType> blks; 87 88 /** The number of sets in the cache. */ 89 const unsigned numSets; 90 91 /** Whether tags and data are accessed sequentially. */ 92 const bool sequentialAccess; 93 94 /** The cache sets. */ 95 std::vector<SetType> sets; 96 97 /** The amount to shift the address to get the set. */ 98 int setShift; 99 /** The amount to shift the address to get the tag. */ 100 int tagShift; 101 /** Mask out all bits that aren't part of the set index. */ 102 unsigned setMask; 103 104 /** Replacement policy */ 105 BaseReplacementPolicy *replacementPolicy; 106 107 public: 108 109 /** Convenience typedef. */ 110 typedef BaseSetAssocParams Params; 111 112 /** 113 * Construct and initialize this tag store. 114 */ 115 BaseSetAssoc(const Params *p); 116 117 /** 118 * Destructor 119 */ 120 virtual ~BaseSetAssoc() {}; 121 122 /** 123 * Find the cache block given set and way 124 * @param set The set of the block. 125 * @param way The way of the block. 126 * @return The cache block. 127 */ 128 CacheBlk *findBlockBySetAndWay(int set, int way) const override; 129 130 /** 131 * Access block and update replacement data. May not succeed, in which case 132 * nullptr is returned. This has all the implications of a cache 133 * access and should only be used as such. Returns the access latency as a 134 * side effect. 135 * @param addr The address to find. 136 * @param is_secure True if the target memory space is secure. 137 * @param lat The access latency. 138 * @return Pointer to the cache block if found. 139 */ 140 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 141 { 142 BlkType *blk = findBlock(addr, is_secure); 143 144 // Access all tags in parallel, hence one in each way. The data side 145 // either accesses all blocks in parallel, or one block sequentially on 146 // a hit. Sequential access with a miss doesn't access data. 147 tagAccesses += allocAssoc; 148 if (sequentialAccess) { 149 if (blk != nullptr) { 150 dataAccesses += 1; 151 } 152 } else { 153 dataAccesses += allocAssoc; 154 } 155 156 if (blk != nullptr) { 157 // If a cache hit 158 lat = accessLatency; 159 // Check if the block to be accessed is available. If not, 160 // apply the accessLatency on top of block->whenReady. 161 if (blk->whenReady > curTick() && 162 cache->ticksToCycles(blk->whenReady - curTick()) > 163 accessLatency) { 164 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 165 accessLatency; 166 } 167 168 // Update replacement data of accessed block 169 replacementPolicy->touch(blk); 170 } else { 171 // If a cache miss 172 lat = lookupLatency; 173 } 174 175 return blk; 176 } 177 178 /** 179 * Finds the given address in the cache, do not update replacement data. 180 * i.e. This is a no-side-effect find of a block. 181 * @param addr The address to find. 182 * @param is_secure True if the target memory space is secure. 183 * @param asid The address space ID. 184 * @return Pointer to the cache block if found. 185 */ 186 CacheBlk* findBlock(Addr addr, bool is_secure) const override; 187 188 /** 189 * Find replacement victim based on address. 190 * 191 * @param addr Address to find a victim for. 192 * @return Cache block to be replaced. 193 */ 194 CacheBlk* findVictim(Addr addr) override 195 { 196 // Choose replacement victim from replacement candidates 197 return replacementPolicy->getVictim(getPossibleLocations(addr)); 198 } 199 200 /** 201 * Find all possible block locations for insertion and replacement of 202 * an address. Should be called immediately before ReplacementPolicy's 203 * findVictim() not to break cache resizing. 204 * Returns blocks in all ways belonging to the set of the address. 205 * 206 * @param addr The addr to a find possible locations for. 207 * @return The possible locations. 208 */ 209 const std::vector<CacheBlk*> getPossibleLocations(Addr addr) 210 { 211 return sets[extractSet(addr)].blks; 212 } 213 214 /**
|