1/* 2 * Copyright (c) 2012-2014,2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 50 unchanged lines hidden (view full) --- 59#include "mem/cache/tags/cacheset.hh" 60#include "mem/packet.hh" 61#include "params/BaseSetAssoc.hh" 62 63/** 64 * A BaseSetAssoc cache tag store. 65 * @sa \ref gem5MemorySystem "gem5 Memory System" 66 * |
67 * The BaseSetAssoc placement policy divides the cache into s sets of w 68 * cache lines (ways). A cache line is mapped onto a set, and can be placed 69 * into any of the ways of this set. |
70 */ 71class BaseSetAssoc : public BaseTags 72{ 73 public: 74 /** Typedef the block type used in this tag store. */ 75 typedef CacheBlk BlkType; 76 /** Typedef the set type used in this tag store. */ 77 typedef CacheSet<CacheBlk> SetType; --- 21 unchanged lines hidden (view full) --- 99 100 /** The amount to shift the address to get the set. */ 101 int setShift; 102 /** The amount to shift the address to get the tag. */ 103 int tagShift; 104 /** Mask out all bits that aren't part of the set index. */ 105 unsigned setMask; 106 |
107 /** Replacement policy */ 108 BaseReplacementPolicy *replacementPolicy; |
109 |
110 public: 111 |
112 /** Convenience typedef. */ 113 typedef BaseSetAssocParams Params; 114 115 /** 116 * Construct and initialize this tag store. 117 */ 118 BaseSetAssoc(const Params *p); 119 --- 42 unchanged lines hidden (view full) --- 162 // Check if the block to be accessed is available. If not, 163 // apply the accessLatency on top of block->whenReady. 164 if (blk->whenReady > curTick() && 165 cache->ticksToCycles(blk->whenReady - curTick()) > 166 accessLatency) { 167 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 168 accessLatency; 169 } |
170 171 // Update replacement data of accessed block 172 replacementPolicy->touch(blk); |
173 } else { 174 // If a cache miss 175 lat = lookupLatency; 176 } 177 178 return blk; 179 } 180 181 /** 182 * Finds the given address in the cache, do not update replacement data. 183 * i.e. This is a no-side-effect find of a block. 184 * @param addr The address to find. 185 * @param is_secure True if the target memory space is secure. 186 * @param asid The address space ID. 187 * @return Pointer to the cache block if found. 188 */ 189 CacheBlk* findBlock(Addr addr, bool is_secure) const override; 190 191 /** |
192 * Find replacement victim based on address. 193 * 194 * @param addr Address to find a victim for. 195 * @return Cache block to be replaced. |
196 */ 197 CacheBlk* findVictim(Addr addr) override 198 { |
199 // Choose replacement victim from replacement candidates 200 return replacementPolicy->getVictim(getPossibleLocations(addr)); 201 } |
202 |
203 /** 204 * Find all possible block locations for insertion and replacement of 205 * an address. Should be called immediately before ReplacementPolicy's 206 * findVictim() not to break cache resizing. 207 * Returns blocks in all ways belonging to the set of the address. 208 * 209 * @param addr The addr to a find possible locations for. 210 * @return The possible locations. 211 */ 212 const std::vector<CacheBlk*> getPossibleLocations(Addr addr) 213 { 214 return sets[extractSet(addr)].blks; |
215 } 216 217 /** 218 * Insert the new block into the cache. 219 * @param pkt Packet holding the address to update 220 * @param blk The block to update. 221 */ 222 void insertBlock(PacketPtr pkt, CacheBlk *blk) override --- 18 unchanged lines hidden (view full) --- 241 totalRefs += blk->refCount; 242 ++sampledRefs; 243 244 invalidate(blk); 245 blk->invalidate(); 246 } 247 248 // Previous block, if existed, has been removed, and now we have |
249 // to insert the new one |
250 tagsInUse++; |
251 252 // Set tag for new block. Caller is responsible for setting status. 253 blk->tag = extractTag(addr); 254 255 // deal with what we are bringing in 256 assert(master_id < cache->system->maxMasters()); 257 occupancies[master_id]++; 258 blk->srcMasterId = master_id; 259 blk->task_id = task_id; |
260 261 // We only need to write into one tag and one data block. 262 tagAccesses += 1; 263 dataAccesses += 1; |
264 265 replacementPolicy->reset(blk); |
266 } 267 268 /** 269 * Limit the allocation for the cache ways. 270 * @param ways The maximum number of ways available for replacement. 271 */ 272 virtual void setWayAllocationMax(int ways) override 273 { --- 80 unchanged lines hidden --- |