1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <functional>
52#include <string>
53#include <vector>
54
55#include "base/logging.hh"
56#include "base/types.hh"
57#include "debug/CacheRepl.hh"
58#include "mem/cache/base.hh"
59#include "mem/cache/blk.hh"
60#include "mem/cache/replacement_policies/base.hh"
61#include "mem/cache/tags/base.hh"
| 1/*
2 * Copyright (c) 2012-2014,2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Declaration of a base set associative tag store.
46 */
47
48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
50
51#include <functional>
52#include <string>
53#include <vector>
54
55#include "base/logging.hh"
56#include "base/types.hh"
57#include "debug/CacheRepl.hh"
58#include "mem/cache/base.hh"
59#include "mem/cache/blk.hh"
60#include "mem/cache/replacement_policies/base.hh"
61#include "mem/cache/tags/base.hh"
|
| 62#include "mem/cache/tags/indexing_policies/base.hh"
|
62#include "params/BaseSetAssoc.hh"
63
64/**
| 63#include "params/BaseSetAssoc.hh"
64
65/**
|
65 * A BaseSetAssoc cache tag store.
| 66 * A basic cache tag store.
|
66 * @sa \ref gem5MemorySystem "gem5 Memory System"
67 *
68 * The BaseSetAssoc placement policy divides the cache into s sets of w
| 67 * @sa \ref gem5MemorySystem "gem5 Memory System"
68 *
69 * The BaseSetAssoc placement policy divides the cache into s sets of w
|
69 * cache lines (ways). A cache line is mapped onto a set, and can be placed
70 * into any of the ways of this set.
| 70 * cache lines (ways).
|
71 */
72class BaseSetAssoc : public BaseTags
73{
74 public:
75 /** Typedef the block type used in this tag store. */
76 typedef CacheBlk BlkType;
| 71 */
72class BaseSetAssoc : public BaseTags
73{
74 public:
75 /** Typedef the block type used in this tag store. */
76 typedef CacheBlk BlkType;
|
77 /** Typedef the set type used in this tag store. */
78 typedef std::vector<CacheBlk*> SetType;
| |
79
80 protected:
| 77
78 protected:
|
81 /** The associativity of the cache. */
82 const unsigned assoc;
| |
83 /** The allocatable associativity of the cache (alloc mask). */
84 unsigned allocAssoc;
85
86 /** The cache blocks. */
87 std::vector<BlkType> blks;
88
| 79 /** The allocatable associativity of the cache (alloc mask). */
80 unsigned allocAssoc;
81
82 /** The cache blocks. */
83 std::vector<BlkType> blks;
84
|
89 /** The number of sets in the cache. */
90 const unsigned numSets;
91
| |
92 /** Whether tags and data are accessed sequentially. */
93 const bool sequentialAccess;
94
| 85 /** Whether tags and data are accessed sequentially. */
86 const bool sequentialAccess;
87
|
95 /** The cache sets. */
96 std::vector<SetType> sets;
97
98 /** The amount to shift the address to get the set. */
99 int setShift;
100 /** The amount to shift the address to get the tag. */
101 int tagShift;
102 /** Mask out all bits that aren't part of the set index. */
103 unsigned setMask;
104
| |
105 /** Replacement policy */
106 BaseReplacementPolicy *replacementPolicy;
107
| 88 /** Replacement policy */
89 BaseReplacementPolicy *replacementPolicy;
90
|
108 /**
109 * Find all possible block locations for insertion and replacement of
110 * an address. Should be called immediately before ReplacementPolicy's
111 * findVictim() not to break cache resizing.
112 * Returns blocks in all ways belonging to the set of the address.
113 *
114 * @param addr The addr to a find possible locations for.
115 * @return The possible locations.
116 */
117 std::vector<ReplaceableEntry*> getPossibleLocations(const Addr addr) const
118 override
119 {
120 std::vector<ReplaceableEntry*> locations;
121 for (const auto& blk : sets[extractSet(addr)]) {
122 locations.push_back(static_cast<ReplaceableEntry*>(blk));
123 }
124 return locations;
125 }
126
| |
127 public:
128 /** Convenience typedef. */
129 typedef BaseSetAssocParams Params;
130
131 /**
132 * Construct and initialize this tag store.
133 */
134 BaseSetAssoc(const Params *p);
135
136 /**
137 * Destructor
138 */
139 virtual ~BaseSetAssoc() {};
140
141 /**
142 * Initialize blocks and set the parent cache back pointer.
143 *
144 * @param _cache Pointer to parent cache.
145 */
146 void init(BaseCache *_cache) override;
147
148 /**
149 * This function updates the tags when a block is invalidated. It also
150 * updates the replacement data.
151 *
152 * @param blk The block to invalidate.
153 */
154 void invalidate(CacheBlk *blk) override;
155
156 /**
157 * Access block and update replacement data. May not succeed, in which case
158 * nullptr is returned. This has all the implications of a cache
159 * access and should only be used as such. Returns the access latency as a
160 * side effect.
161 * @param addr The address to find.
162 * @param is_secure True if the target memory space is secure.
163 * @param lat The access latency.
164 * @return Pointer to the cache block if found.
165 */
166 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
167 {
168 BlkType *blk = findBlock(addr, is_secure);
169
170 // Access all tags in parallel, hence one in each way. The data side
171 // either accesses all blocks in parallel, or one block sequentially on
172 // a hit. Sequential access with a miss doesn't access data.
173 tagAccesses += allocAssoc;
174 if (sequentialAccess) {
175 if (blk != nullptr) {
176 dataAccesses += 1;
177 }
178 } else {
179 dataAccesses += allocAssoc;
180 }
181
182 if (blk != nullptr) {
183 // If a cache hit
184 lat = accessLatency;
185 // Check if the block to be accessed is available. If not,
186 // apply the accessLatency on top of block->whenReady.
187 if (blk->whenReady > curTick() &&
188 cache->ticksToCycles(blk->whenReady - curTick()) >
189 accessLatency) {
190 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
191 accessLatency;
192 }
193
194 // Update number of references to accessed block
195 blk->refCount++;
196
197 // Update replacement data of accessed block
198 replacementPolicy->touch(blk->replacementData);
199 } else {
200 // If a cache miss
201 lat = lookupLatency;
202 }
203
204 return blk;
205 }
206
207 /**
| 91 public:
92 /** Convenience typedef. */
93 typedef BaseSetAssocParams Params;
94
95 /**
96 * Construct and initialize this tag store.
97 */
98 BaseSetAssoc(const Params *p);
99
100 /**
101 * Destructor
102 */
103 virtual ~BaseSetAssoc() {};
104
105 /**
106 * Initialize blocks and set the parent cache back pointer.
107 *
108 * @param _cache Pointer to parent cache.
109 */
110 void init(BaseCache *_cache) override;
111
112 /**
113 * This function updates the tags when a block is invalidated. It also
114 * updates the replacement data.
115 *
116 * @param blk The block to invalidate.
117 */
118 void invalidate(CacheBlk *blk) override;
119
120 /**
121 * Access block and update replacement data. May not succeed, in which case
122 * nullptr is returned. This has all the implications of a cache
123 * access and should only be used as such. Returns the access latency as a
124 * side effect.
125 * @param addr The address to find.
126 * @param is_secure True if the target memory space is secure.
127 * @param lat The access latency.
128 * @return Pointer to the cache block if found.
129 */
130 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
131 {
132 BlkType *blk = findBlock(addr, is_secure);
133
134 // Access all tags in parallel, hence one in each way. The data side
135 // either accesses all blocks in parallel, or one block sequentially on
136 // a hit. Sequential access with a miss doesn't access data.
137 tagAccesses += allocAssoc;
138 if (sequentialAccess) {
139 if (blk != nullptr) {
140 dataAccesses += 1;
141 }
142 } else {
143 dataAccesses += allocAssoc;
144 }
145
146 if (blk != nullptr) {
147 // If a cache hit
148 lat = accessLatency;
149 // Check if the block to be accessed is available. If not,
150 // apply the accessLatency on top of block->whenReady.
151 if (blk->whenReady > curTick() &&
152 cache->ticksToCycles(blk->whenReady - curTick()) >
153 accessLatency) {
154 lat = cache->ticksToCycles(blk->whenReady - curTick()) +
155 accessLatency;
156 }
157
158 // Update number of references to accessed block
159 blk->refCount++;
160
161 // Update replacement data of accessed block
162 replacementPolicy->touch(blk->replacementData);
163 } else {
164 // If a cache miss
165 lat = lookupLatency;
166 }
167
168 return blk;
169 }
170
171 /**
|
208 * Find a block given set and way.
209 *
210 * @param set The set of the block.
211 * @param way The way of the block.
212 * @return The block.
213 */
214 ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override;
215
216 /**
| |
217 * Find replacement victim based on address. The list of evicted blocks
218 * only contains the victim.
219 *
220 * @param addr Address to find a victim for.
221 * @param is_secure True if the target memory space is secure.
222 * @param evict_blks Cache blocks to be evicted.
223 * @return Cache block to be replaced.
224 */
225 CacheBlk* findVictim(Addr addr, const bool is_secure,
226 std::vector<CacheBlk*>& evict_blks) const override
227 {
| 172 * Find replacement victim based on address. The list of evicted blocks
173 * only contains the victim.
174 *
175 * @param addr Address to find a victim for.
176 * @param is_secure True if the target memory space is secure.
177 * @param evict_blks Cache blocks to be evicted.
178 * @return Cache block to be replaced.
179 */
180 CacheBlk* findVictim(Addr addr, const bool is_secure,
181 std::vector<CacheBlk*>& evict_blks) const override
182 {
|
228 // Get possible locations for the victim block
229 std::vector<ReplaceableEntry*> locations = getPossibleLocations(addr);
| 183 // Get possible entries to be victimized
184 const std::vector<ReplaceableEntry*> entries =
185 indexingPolicy->getPossibleEntries(addr);
|
230
231 // Choose replacement victim from replacement candidates
232 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim(
| 186
187 // Choose replacement victim from replacement candidates
188 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim(
|
233 std::vector<ReplaceableEntry*>(
234 locations.begin(), locations.end())));
| 189 entries));
|
235
236 // There is only one eviction for this replacement
237 evict_blks.push_back(victim);
238
239 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
240 victim->getSet(), victim->getWay());
241
242 return victim;
243 }
244
245 /**
246 * Insert the new block into the cache and update replacement data.
247 *
248 * @param addr Address of the block.
249 * @param is_secure Whether the block is in secure space or not.
250 * @param src_master_ID The source requestor ID.
251 * @param task_ID The new task ID.
252 * @param blk The block to update.
253 */
254 void insertBlock(const Addr addr, const bool is_secure,
255 const int src_master_ID, const uint32_t task_ID,
256 CacheBlk *blk) override
257 {
258 // Insert block
259 BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk);
260
261 // Increment tag counter
262 tagsInUse++;
263
264 // Update replacement policy
265 replacementPolicy->reset(blk->replacementData);
266 }
267
268 /**
269 * Limit the allocation for the cache ways.
270 * @param ways The maximum number of ways available for replacement.
271 */
272 virtual void setWayAllocationMax(int ways) override
273 {
274 fatal_if(ways < 1, "Allocation limit must be greater than zero");
275 allocAssoc = ways;
276 }
277
278 /**
279 * Get the way allocation mask limit.
280 * @return The maximum number of ways available for replacement.
281 */
282 virtual int getWayAllocationMax() const override
283 {
284 return allocAssoc;
285 }
286
287 /**
| 190
191 // There is only one eviction for this replacement
192 evict_blks.push_back(victim);
193
194 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
195 victim->getSet(), victim->getWay());
196
197 return victim;
198 }
199
200 /**
201 * Insert the new block into the cache and update replacement data.
202 *
203 * @param addr Address of the block.
204 * @param is_secure Whether the block is in secure space or not.
205 * @param src_master_ID The source requestor ID.
206 * @param task_ID The new task ID.
207 * @param blk The block to update.
208 */
209 void insertBlock(const Addr addr, const bool is_secure,
210 const int src_master_ID, const uint32_t task_ID,
211 CacheBlk *blk) override
212 {
213 // Insert block
214 BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk);
215
216 // Increment tag counter
217 tagsInUse++;
218
219 // Update replacement policy
220 replacementPolicy->reset(blk->replacementData);
221 }
222
223 /**
224 * Limit the allocation for the cache ways.
225 * @param ways The maximum number of ways available for replacement.
226 */
227 virtual void setWayAllocationMax(int ways) override
228 {
229 fatal_if(ways < 1, "Allocation limit must be greater than zero");
230 allocAssoc = ways;
231 }
232
233 /**
234 * Get the way allocation mask limit.
235 * @return The maximum number of ways available for replacement.
236 */
237 virtual int getWayAllocationMax() const override
238 {
239 return allocAssoc;
240 }
241
242 /**
|
288 * Generate the tag from the given address.
289 * @param addr The address to get the tag from.
290 * @return The tag of the address.
291 */
292 Addr extractTag(Addr addr) const override
293 {
294 return (addr >> tagShift);
295 }
296
297 /**
298 * Regenerate the block address from the tag and set.
| 243 * Regenerate the block address from the tag and indexing location.
|
299 *
300 * @param block The block.
301 * @return the block address.
302 */
303 Addr regenerateBlkAddr(const CacheBlk* blk) const override
304 {
| 244 *
245 * @param block The block.
246 * @return the block address.
247 */
248 Addr regenerateBlkAddr(const CacheBlk* blk) const override
249 {
|
305 const Addr set = blk->getSet() << setShift;
306 return ((blk->tag << tagShift) | set);
| 250 return indexingPolicy->regenerateAddr(blk->tag, blk);
|
307 }
308
309 void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
310 for (CacheBlk& blk : blks) {
311 visitor(blk);
312 }
313 }
314
315 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override {
316 for (CacheBlk& blk : blks) {
317 if (visitor(blk)) {
318 return true;
319 }
320 }
321 return false;
322 }
| 251 }
252
253 void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
254 for (CacheBlk& blk : blks) {
255 visitor(blk);
256 }
257 }
258
259 bool anyBlk(std::function<bool(CacheBlk &)> visitor) override {
260 for (CacheBlk& blk : blks) {
261 if (visitor(blk)) {
262 return true;
263 }
264 }
265 return false;
266 }
|
323
324 private:
325 /**
326 * Calculate the set index from the address.
327 *
328 * @param addr The address to get the set from.
329 * @return The set index of the address.
330 */
331 int extractSet(Addr addr) const
332 {
333 return ((addr >> setShift) & setMask);
334 }
| |
335};
336
337#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
| 267};
268
269#endif //__MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__
|