1/* 2 * Copyright (c) 2012-2014,2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a base set associative tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 50 51#include <functional> 52#include <string> 53#include <vector> 54 55#include "base/logging.hh" 56#include "base/types.hh" 57#include "debug/CacheRepl.hh" 58#include "mem/cache/base.hh" 59#include "mem/cache/blk.hh" 60#include "mem/cache/replacement_policies/base.hh" 61#include "mem/cache/tags/base.hh" 62#include "params/BaseSetAssoc.hh" 63 64/** 65 * A BaseSetAssoc cache tag store. 66 * @sa \ref gem5MemorySystem "gem5 Memory System" 67 * 68 * The BaseSetAssoc placement policy divides the cache into s sets of w 69 * cache lines (ways). A cache line is mapped onto a set, and can be placed 70 * into any of the ways of this set. 71 */ 72class BaseSetAssoc : public BaseTags 73{ 74 public: 75 /** Typedef the block type used in this tag store. */ 76 typedef CacheBlk BlkType; 77 /** Typedef the set type used in this tag store. */ 78 typedef std::vector<CacheBlk*> SetType; 79 80 protected: 81 /** The associativity of the cache. */ 82 const unsigned assoc; 83 /** The allocatable associativity of the cache (alloc mask). */ 84 unsigned allocAssoc; 85 86 /** The cache blocks. */ 87 std::vector<BlkType> blks; 88 89 /** The number of sets in the cache. */ 90 const unsigned numSets; 91 92 /** Whether tags and data are accessed sequentially. */ 93 const bool sequentialAccess; 94 95 /** The cache sets. */ 96 std::vector<SetType> sets; 97 98 /** The amount to shift the address to get the set. */ 99 int setShift; 100 /** The amount to shift the address to get the tag. */ 101 int tagShift; 102 /** Mask out all bits that aren't part of the set index. */ 103 unsigned setMask; 104 105 /** Replacement policy */ 106 BaseReplacementPolicy *replacementPolicy; 107 108 /** 109 * Find all possible block locations for insertion and replacement of 110 * an address. Should be called immediately before ReplacementPolicy's 111 * findVictim() not to break cache resizing. 112 * Returns blocks in all ways belonging to the set of the address. 113 * 114 * @param addr The addr to a find possible locations for. 115 * @return The possible locations. 116 */ 117 std::vector<ReplaceableEntry*> getPossibleLocations(const Addr addr) const 118 override 119 { 120 std::vector<ReplaceableEntry*> locations; 121 for (const auto& blk : sets[extractSet(addr)]) { 122 locations.push_back(static_cast<ReplaceableEntry*>(blk)); 123 } 124 return locations; 125 } 126 127 public: 128 /** Convenience typedef. */ 129 typedef BaseSetAssocParams Params; 130 131 /** 132 * Construct and initialize this tag store. 133 */ 134 BaseSetAssoc(const Params *p); 135 136 /** 137 * Destructor 138 */ 139 virtual ~BaseSetAssoc() {}; 140 141 /** 142 * Initialize blocks and set the parent cache back pointer. 143 * 144 * @param _cache Pointer to parent cache. 145 */ 146 void init(BaseCache *_cache) override; 147 148 /** 149 * This function updates the tags when a block is invalidated. It also 150 * updates the replacement data. 151 * 152 * @param blk The block to invalidate. 153 */ 154 void invalidate(CacheBlk *blk) override; 155 156 /** 157 * Access block and update replacement data. May not succeed, in which case 158 * nullptr is returned. This has all the implications of a cache 159 * access and should only be used as such. Returns the access latency as a 160 * side effect. 161 * @param addr The address to find. 162 * @param is_secure True if the target memory space is secure. 163 * @param lat The access latency. 164 * @return Pointer to the cache block if found. 165 */ 166 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 167 { 168 BlkType *blk = findBlock(addr, is_secure); 169 170 // Access all tags in parallel, hence one in each way. The data side 171 // either accesses all blocks in parallel, or one block sequentially on 172 // a hit. Sequential access with a miss doesn't access data. 173 tagAccesses += allocAssoc; 174 if (sequentialAccess) { 175 if (blk != nullptr) { 176 dataAccesses += 1; 177 } 178 } else { 179 dataAccesses += allocAssoc; 180 } 181 182 if (blk != nullptr) { 183 // If a cache hit 184 lat = accessLatency; 185 // Check if the block to be accessed is available. If not, 186 // apply the accessLatency on top of block->whenReady. 187 if (blk->whenReady > curTick() && 188 cache->ticksToCycles(blk->whenReady - curTick()) > 189 accessLatency) { 190 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 191 accessLatency; 192 } 193 194 // Update number of references to accessed block 195 blk->refCount++; 196 197 // Update replacement data of accessed block 198 replacementPolicy->touch(blk->replacementData); 199 } else { 200 // If a cache miss 201 lat = lookupLatency; 202 } 203 204 return blk; 205 } 206 207 /** 208 * Find a block given set and way. 209 * 210 * @param set The set of the block. 211 * @param way The way of the block. 212 * @return The block. 213 */ 214 ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override; 215 216 /** 217 * Find replacement victim based on address. The list of evicted blocks 218 * only contains the victim. 219 * 220 * @param addr Address to find a victim for. 221 * @param is_secure True if the target memory space is secure. 222 * @param evict_blks Cache blocks to be evicted. 223 * @return Cache block to be replaced. 224 */ 225 CacheBlk* findVictim(Addr addr, const bool is_secure, 226 std::vector<CacheBlk*>& evict_blks) const override 227 { 228 // Get possible locations for the victim block 229 std::vector<ReplaceableEntry*> locations = getPossibleLocations(addr); 230 231 // Choose replacement victim from replacement candidates 232 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim( 233 std::vector<ReplaceableEntry*>( 234 locations.begin(), locations.end()))); 235 236 // There is only one eviction for this replacement 237 evict_blks.push_back(victim); 238 239 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
| 1/* 2 * Copyright (c) 2012-2014,2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005,2014 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a base set associative tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 49#define __MEM_CACHE_TAGS_BASE_SET_ASSOC_HH__ 50 51#include <functional> 52#include <string> 53#include <vector> 54 55#include "base/logging.hh" 56#include "base/types.hh" 57#include "debug/CacheRepl.hh" 58#include "mem/cache/base.hh" 59#include "mem/cache/blk.hh" 60#include "mem/cache/replacement_policies/base.hh" 61#include "mem/cache/tags/base.hh" 62#include "params/BaseSetAssoc.hh" 63 64/** 65 * A BaseSetAssoc cache tag store. 66 * @sa \ref gem5MemorySystem "gem5 Memory System" 67 * 68 * The BaseSetAssoc placement policy divides the cache into s sets of w 69 * cache lines (ways). A cache line is mapped onto a set, and can be placed 70 * into any of the ways of this set. 71 */ 72class BaseSetAssoc : public BaseTags 73{ 74 public: 75 /** Typedef the block type used in this tag store. */ 76 typedef CacheBlk BlkType; 77 /** Typedef the set type used in this tag store. */ 78 typedef std::vector<CacheBlk*> SetType; 79 80 protected: 81 /** The associativity of the cache. */ 82 const unsigned assoc; 83 /** The allocatable associativity of the cache (alloc mask). */ 84 unsigned allocAssoc; 85 86 /** The cache blocks. */ 87 std::vector<BlkType> blks; 88 89 /** The number of sets in the cache. */ 90 const unsigned numSets; 91 92 /** Whether tags and data are accessed sequentially. */ 93 const bool sequentialAccess; 94 95 /** The cache sets. */ 96 std::vector<SetType> sets; 97 98 /** The amount to shift the address to get the set. */ 99 int setShift; 100 /** The amount to shift the address to get the tag. */ 101 int tagShift; 102 /** Mask out all bits that aren't part of the set index. */ 103 unsigned setMask; 104 105 /** Replacement policy */ 106 BaseReplacementPolicy *replacementPolicy; 107 108 /** 109 * Find all possible block locations for insertion and replacement of 110 * an address. Should be called immediately before ReplacementPolicy's 111 * findVictim() not to break cache resizing. 112 * Returns blocks in all ways belonging to the set of the address. 113 * 114 * @param addr The addr to a find possible locations for. 115 * @return The possible locations. 116 */ 117 std::vector<ReplaceableEntry*> getPossibleLocations(const Addr addr) const 118 override 119 { 120 std::vector<ReplaceableEntry*> locations; 121 for (const auto& blk : sets[extractSet(addr)]) { 122 locations.push_back(static_cast<ReplaceableEntry*>(blk)); 123 } 124 return locations; 125 } 126 127 public: 128 /** Convenience typedef. */ 129 typedef BaseSetAssocParams Params; 130 131 /** 132 * Construct and initialize this tag store. 133 */ 134 BaseSetAssoc(const Params *p); 135 136 /** 137 * Destructor 138 */ 139 virtual ~BaseSetAssoc() {}; 140 141 /** 142 * Initialize blocks and set the parent cache back pointer. 143 * 144 * @param _cache Pointer to parent cache. 145 */ 146 void init(BaseCache *_cache) override; 147 148 /** 149 * This function updates the tags when a block is invalidated. It also 150 * updates the replacement data. 151 * 152 * @param blk The block to invalidate. 153 */ 154 void invalidate(CacheBlk *blk) override; 155 156 /** 157 * Access block and update replacement data. May not succeed, in which case 158 * nullptr is returned. This has all the implications of a cache 159 * access and should only be used as such. Returns the access latency as a 160 * side effect. 161 * @param addr The address to find. 162 * @param is_secure True if the target memory space is secure. 163 * @param lat The access latency. 164 * @return Pointer to the cache block if found. 165 */ 166 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override 167 { 168 BlkType *blk = findBlock(addr, is_secure); 169 170 // Access all tags in parallel, hence one in each way. The data side 171 // either accesses all blocks in parallel, or one block sequentially on 172 // a hit. Sequential access with a miss doesn't access data. 173 tagAccesses += allocAssoc; 174 if (sequentialAccess) { 175 if (blk != nullptr) { 176 dataAccesses += 1; 177 } 178 } else { 179 dataAccesses += allocAssoc; 180 } 181 182 if (blk != nullptr) { 183 // If a cache hit 184 lat = accessLatency; 185 // Check if the block to be accessed is available. If not, 186 // apply the accessLatency on top of block->whenReady. 187 if (blk->whenReady > curTick() && 188 cache->ticksToCycles(blk->whenReady - curTick()) > 189 accessLatency) { 190 lat = cache->ticksToCycles(blk->whenReady - curTick()) + 191 accessLatency; 192 } 193 194 // Update number of references to accessed block 195 blk->refCount++; 196 197 // Update replacement data of accessed block 198 replacementPolicy->touch(blk->replacementData); 199 } else { 200 // If a cache miss 201 lat = lookupLatency; 202 } 203 204 return blk; 205 } 206 207 /** 208 * Find a block given set and way. 209 * 210 * @param set The set of the block. 211 * @param way The way of the block. 212 * @return The block. 213 */ 214 ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override; 215 216 /** 217 * Find replacement victim based on address. The list of evicted blocks 218 * only contains the victim. 219 * 220 * @param addr Address to find a victim for. 221 * @param is_secure True if the target memory space is secure. 222 * @param evict_blks Cache blocks to be evicted. 223 * @return Cache block to be replaced. 224 */ 225 CacheBlk* findVictim(Addr addr, const bool is_secure, 226 std::vector<CacheBlk*>& evict_blks) const override 227 { 228 // Get possible locations for the victim block 229 std::vector<ReplaceableEntry*> locations = getPossibleLocations(addr); 230 231 // Choose replacement victim from replacement candidates 232 CacheBlk* victim = static_cast<CacheBlk*>(replacementPolicy->getVictim( 233 std::vector<ReplaceableEntry*>( 234 locations.begin(), locations.end()))); 235 236 // There is only one eviction for this replacement 237 evict_blks.push_back(victim); 238 239 DPRINTF(CacheRepl, "set %x, way %x: selecting blk for replacement\n",
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241 242 return victim; 243 } 244 245 /** 246 * Insert the new block into the cache and update replacement data. 247 * 248 * @param addr Address of the block. 249 * @param is_secure Whether the block is in secure space or not. 250 * @param src_master_ID The source requestor ID. 251 * @param task_ID The new task ID. 252 * @param blk The block to update. 253 */ 254 void insertBlock(const Addr addr, const bool is_secure, 255 const int src_master_ID, const uint32_t task_ID, 256 CacheBlk *blk) override 257 { 258 // Insert block 259 BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk); 260 261 // Increment tag counter 262 tagsInUse++; 263 264 // Update replacement policy 265 replacementPolicy->reset(blk->replacementData); 266 } 267 268 /** 269 * Limit the allocation for the cache ways. 270 * @param ways The maximum number of ways available for replacement. 271 */ 272 virtual void setWayAllocationMax(int ways) override 273 { 274 fatal_if(ways < 1, "Allocation limit must be greater than zero"); 275 allocAssoc = ways; 276 } 277 278 /** 279 * Get the way allocation mask limit. 280 * @return The maximum number of ways available for replacement. 281 */ 282 virtual int getWayAllocationMax() const override 283 { 284 return allocAssoc; 285 } 286 287 /** 288 * Generate the tag from the given address. 289 * @param addr The address to get the tag from. 290 * @return The tag of the address. 291 */ 292 Addr extractTag(Addr addr) const override 293 { 294 return (addr >> tagShift); 295 } 296 297 /** 298 * Regenerate the block address from the tag and set. 299 * 300 * @param block The block. 301 * @return the block address. 302 */ 303 Addr regenerateBlkAddr(const CacheBlk* blk) const override 304 {
| 241 242 return victim; 243 } 244 245 /** 246 * Insert the new block into the cache and update replacement data. 247 * 248 * @param addr Address of the block. 249 * @param is_secure Whether the block is in secure space or not. 250 * @param src_master_ID The source requestor ID. 251 * @param task_ID The new task ID. 252 * @param blk The block to update. 253 */ 254 void insertBlock(const Addr addr, const bool is_secure, 255 const int src_master_ID, const uint32_t task_ID, 256 CacheBlk *blk) override 257 { 258 // Insert block 259 BaseTags::insertBlock(addr, is_secure, src_master_ID, task_ID, blk); 260 261 // Increment tag counter 262 tagsInUse++; 263 264 // Update replacement policy 265 replacementPolicy->reset(blk->replacementData); 266 } 267 268 /** 269 * Limit the allocation for the cache ways. 270 * @param ways The maximum number of ways available for replacement. 271 */ 272 virtual void setWayAllocationMax(int ways) override 273 { 274 fatal_if(ways < 1, "Allocation limit must be greater than zero"); 275 allocAssoc = ways; 276 } 277 278 /** 279 * Get the way allocation mask limit. 280 * @return The maximum number of ways available for replacement. 281 */ 282 virtual int getWayAllocationMax() const override 283 { 284 return allocAssoc; 285 } 286 287 /** 288 * Generate the tag from the given address. 289 * @param addr The address to get the tag from. 290 * @return The tag of the address. 291 */ 292 Addr extractTag(Addr addr) const override 293 { 294 return (addr >> tagShift); 295 } 296 297 /** 298 * Regenerate the block address from the tag and set. 299 * 300 * @param block The block. 301 * @return the block address. 302 */ 303 Addr regenerateBlkAddr(const CacheBlk* blk) const override 304 {
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